MAX5886EGK MAXIM [Maxim Integrated Products], MAX5886EGK Datasheet
MAX5886EGK
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MAX5886EGK Summary of contents
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... Excellent SFDR and IMD Performance SFDR = 76dBc at f IMD = -85dBc at f ACLR = 70dB 2mA to 20mA Full-Scale Output Current o Differential, LVDS-Compatible Digital and Clock Inputs o On-Chip 1.2V Bandgap Reference o Low 130mW Power Dissipation o 68-Pin QFN-EP Package PART MAX5886EGK *EP = Exposed paddle. TOP VIEW Applications N.C. 1 N.C. 2 N.C. 3 N.C. ...
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High Dynamic Performance DAC with Differential LVDS Inputs ABSOLUTE MAXIMUM RATINGS VCLK to AGND................................-0.3V to +3. VCLK to DGND ...............................-0.3V to +3. ...
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High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference analog output, 50Ω double terminated (Figure 7), ...
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High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference analog output, 50Ω double terminated (Figure 7), ...
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High Dynamic Performance DAC with Differential LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) ( VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference analog output, 50Ω double terminated (Figure 7), ...
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High Dynamic Performance DAC with Differential LVDS Inputs ( VCLK = 3.3V, external reference SFDR vs. OUTPUT FREQUENCY (f = 300MHz -6dB FS) CLK OUT 100 I = 20mA ...
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High Dynamic Performance DAC with Differential LVDS Inputs PIN NAME 1–8, 23, 34, N.C. Not connected. Do not connect to these pins. Do not tie these pins together. 35–38 9, 41, 60, 62 DGND Digital Ground Digital ...
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High Dynamic Performance DAC with Differential LVDS Inputs PIN NAME 47 B9N Complementary Data Bit 9 48 B8P Data Bit 8 49 B8N Complementary Data Bit 8 50 B7P Data Bit 7 51 B7N Complementary Data Bit ...
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High Dynamic Performance DAC with Differential LVDS Inputs DV DGND DD 1.2V REFERENCE REFIO FSADJ CLKN CLKP Figure 1. Simplified MAX5886 Block Diagram Table 1. I and R Selection Matrix Based on a Typical 1.200V Reference Voltage ...
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High Dynamic Performance DAC with Differential LVDS Inputs 1.2V REFERENCE 10kΩ REFIO 0.1µF FSADJ CURRENT-STEERING I REF R SET DACREF REF REFIO SET Figure 2. Reference Architecture, Internal Reference Configuration Figure 3 displays ...
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High Dynamic Performance DAC with Differential LVDS Inputs DIGITAL DATA IS LATCHED ON THE RISING EDGE OF CLKP B0 TO B15 SETUP CLKP CLKN IOUT Figure 5. Detailed Timing Relationship ...
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High Dynamic Performance DAC with Differential LVDS Inputs B0–B11 MAX5886 12 AGND DGND Figure 7. Differential to Single-Ended Conversion Using a Wideband RF Transformer AV DV VCLK DD DD IOUTP B0–B11 MAX5886 IOUTN 12 ...
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High Dynamic Performance DAC with Differential LVDS Inputs between the frequency components located within the carrier band. The energy at one end of the carrier band generates IM products with the energy from the oppo- site end ...
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High Dynamic Performance DAC with Differential LVDS Inputs individual carrier must be operated at less than -12dB FS/-18dB FS to avoid waveform clipping. The noise density requirements (Table 2) for a GSM/EDGE-based system can again be derived ...
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High Dynamic Performance DAC with Differential LVDS Inputs O MEASUREMENT BANDWIDTH -30 30kHz 100kHz -60 -70 -73 -75 -80 -90 0.2 0.4 0.6 1.2 1.8 FREQUENCY OFFSET FROM CARRIER (MHz) Figure 11. GSM/EDGE Tx Mask Requirements supply ...
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High Dynamic Performance DAC with Differential LVDS Inputs In this package, the data converter die is attached lead frame with the back of this frame exposed at the package bottom surface, facing the PC ...
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High Dynamic Performance DAC with Differential LVDS Inputs A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to ...
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High Dynamic Performance DAC with Differential LVDS Inputs (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, (The package drawing(s) in this data sheet may not ...