PCM1741/E2K BURR-BROWN [Burr-Brown Corporation], PCM1741/E2K Datasheet - Page 10

• Manufacturer Part Number: PCM1741/E2K
• Description: +3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

10
SERIAL CONTROL INTERFACE
The serial control interface is a 3-wire serial port that
operates asynchronously to the serial audio interface. The
serial control interface is utilized to program the on-chip
mode registers. The control interface includes MD (pin 13),
MC (pin 14), and ML (pin 15). MD is the serial data input,
used to program the mode registers, MC is the serial bit
clock, used to shift data into the control port, and ML is the
control port latch clock.
REGISTER WRITE OPERATION
All write operations for the serial control port use 16-bit data
words. Figure 5 shows the control data word format. The
most significant bit must be a “0”. There are seven bits,
labeled IDX[6:0], that set the register index (or address) for
FIGURE 6. Register Write Operation.
FIGURE 5. Control Data Word Format for MDI.
FIGURE 4. Audio Interface Timing.
LRCK
DATA
BCK
MC
MD
ML
NOTE: (1) f
SYMBOL
t
t
t
t
t
t
t
BCY
BCH
BCL
BL
LB
DS
DH
X
MSB
0
0
t
BCH
S
IDX6
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
LRCK Falling Edge to BCK Rising Edge
IDX5
Register Index (or Address)
t
BCY
BCK Rising Edge to LRCK Edge
IDX4
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
DATA Set Up Time
t
BCL
DATA Hold Time
IDX3
PARAMETER
t
DS
IDX2
IDX1 IDX0
t
t
BL
DH
D7
D7
the write operation. The least significant eight bits, D[7:0],
contain the data to be written to the register specified by
IDX[6:0].
Figure 6 shows the functional timing diagram for writing the
serial control port. ML is held at a logic “1 ” state until a
register needs to be written. To start the register write cycle,
ML is set to logic “0”. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on
MD. After the sixteenth clock cycle has completed, ML is set
to logic “1” to latch the data into the indexed mode control
register.
CONTROL INTERFACE TIMING REQUIREMENTS
See Figure 7 for a detailed timing diagram of the serial
control interface. These timing parameters are critical for
proper control port operation.
D6
D6
D5
MIN
D5
35
35
10
10
10
10
D4
Register Data
t
LB
D4
D3
32, 48, or 64f
D3
D2
MAX
D2
D1
S
(1)
D0
D1
UNITS
LSB
X
D0
ns
ns
ns
ns
ns
ns
X
0
50% of V
50% of V
50% of V
IDX6
PCM1741
DD
DD
DD
SBAS175