PCM1741/E2K BURR-BROWN [Burr-Brown Corporation], PCM1741/E2K Datasheet - Page 8

• Manufacturer Part Number: PCM1741/E2K
• Description: +3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

8
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1741 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modu-
lators. The system clock is applied at the SCK input (pin 16).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator from Texas Instruments is an excellent choice
for providing the PCM1741 system clock.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
FIGURE 1. System Clock Input Timing.
FIGURE 2. Power-On Reset Timing.
NOTE: (1) The 768f
FREQUENCY
SAMPLING
44.1kHz
88.2kHz
16kHz
32kHz
48kHz
96kHz
8kHz
Internal Reset
System Clock
V
DD
S
system clock rate is not supported for f
2.4V
2.0V
1.6V
System Clock
0V
“H”
Don't Care
“L”
11.2896
12.2880
22.5792
24.5760
2.0480
4.0960
8.1920
256f
S
t
SCKL
S
System Clock Pulse Width HIGH t
NOTE: (1) 1/256f
System Clock Pulse Width LOW t
> 64kHz.
t
SCKH
SYSTEM CLOCK FREQUENCY (f
12.2880
16.9344
18.4320
33.8688
36.8640
3.0720
6.1440
384f
S
Reset
1024 System Clocks
, 1/384f
S
POWER-ON RESET FUNCTIONS
The PCM1741 includes a power-on reset function, as shown in
Figure 2. With the system clock active, and V
1.6V to 2.4V), the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time V
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level, or V
the reset period, the internal register is initialized in the next
1/f
continuously, the PCM1741 provides proper analog output
with unit group delay against the input data.
S
S
period and, if SCK, BCK, and LRCK are provided
, 1/512f
DD
System clock pulse
> 2.0V. After the initialization period, the PCM1741
SCKL
SCKH
S
cycle time
, and 1/768f
: 7ns (min)
: 7ns (min)
16.3840
22.5792
24.5760
45.1584
49.1520
(1)
SCLK
4.0960
8.1920
512f
S
.
) (MHz)
S
Reset Removal
2.0V
0.8V
See Note (1)
See Note (1)
DD
12.2880
24.5760
33.8688
36.8640
6.1440
768f
> 2.0V (typical
PCM1741
S
CC
SBAS175
/2. After