AD7277BRM AD [Analog Devices], AD7277BRM Datasheet - Page 15

• Manufacturer Part Number: AD7277BRM
• Description: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
• Manufacturer: AD [Analog Devices]

Digital Inputs
The digital inputs applied to the AD7276/AD7277/
AD7278 are not limited by the maximum ratings which
limit the analog inputs. Instead, the digitals inputs applied
can go to TBDV and are not restricted by the V
limit as on the analog inputs. For example, if the
AD7276/AD7277/AD7278 were operated with a V
3V then 5V logic levels could be used on the digital
inputs. However, it is important to note that the data
output on SDATA will still have 3V logic levels when
V
restricted by the V
supply sequencing issues are avoided. If CS or SCLK are
applied before V
there would be on the analog inputs if a signal greater
than 0.3V was applied prior to V
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount
of total harmonic distortion (THD) that can be
tolerated. The THD will increase as the source
impedance increases and performance will degrade. TPC
7 shows a graph of the Total Harmonic Distortion
versus Analog input frequency for different source
impedances when using a supply voltage of TBD V and
sampling at a rate of 3 MSPS.
Table II provides some typical performance data with
various op-amps used as the input buffer under the same
set-up conditions.
REV. PrF
Preliminary Technical Data
DD
Table II. AD7276 performance for various Input Buffers
= 3V. Another advantage of SCLK and CS not being
Op-amp in the
AD8510
AD8610
AD8519
input buffer
AD8038
SDATA
DD
SCLK
DD
&6
then there is no risk of latch-up as
+ 0.3V limit is the fact that power
AD7276 SNR Performance
TBD dB
TBD dB
TBD dB
TBD dB
TBD kHz Input
PRELIMINARY TECHNICAL DATA
DD
.
1
Figure 12. Normal Mode Operation
DD
DD
+ 0.3V
of
VALID DATA
–15–
MODES OF OPERATION
The mode of operation of the AD7276/AD7277/AD7278
is selected by controlling the logic state of the CS signal
during a conversion. There are two possible modes of
operation, Normal Mode and Power-Down Mode. The
point at which CS is pulled high after the conversion has
been initiated will determine whether the AD7276/
AD7277/AD7278 will enter Power-Down Mode or not.
Similarly, if already in Power-Down then CS can control
whether the device will return to Normal operation or
remain in Power-Down. These modes of operation are
designed to provide flexible power management options.
These options can be chosen to optimize the power dissi-
pation/throughput rate ratio for different application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance as the user does not have to worry about any
power-up times with the AD7276/AD7277/AD7278
remaining fully powered all the time. Figure 12 shows the
general diagram of the operation of the AD7276/AD7277/
AD7278 in this mode.
The conversion is iniated on the falling edge of CS as
described in the Serial Interface section. To ensure the
part remains fully powered up at all times CS must remain
low until at least 10 SCLK falling edges have elapsed after
the falling edge of CS. If CS is brought high any time
after the 10th SCLK falling, the part will remain powered
up but the conversion will be terminated and SDATA will
go back into three-state.
For the AD7276 a minimum of 14 serial clock cycles are
required to complete the conversion and access the
complete conversion result. For the AD7277 and AD7278
a minimum of 12 and 10 serial clock cycles are required
to complete the conversion and access the complete con-
version result, respectively.
CS may idle high until the next conversion or may idle
low until CS returns high sometime prior to the next
conversion (effectively idling CS low).
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the
quiet time, t
10
12
QUIET
14
, has elapsed by bringing CS low again.
AD7276/AD7277/AD7278
16
AD7276/77/78