AD7277BRM AD [Analog Devices], AD7277BRM Datasheet - Page 16

• Manufacturer Part Number: AD7277BRM
• Description: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
• Manufacturer: AD [Analog Devices]

Power-Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and then the ADC is powered down for a relatively long
duration between these bursts of several conversions.
When the AD7276/AD7277/AD7278 is in Power-Down,
all analog circuitry is powered down.
To enter Power-Down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10th falling edge of
SCLK as shown in Figure 13. Once CS has been brought
high in this window of SCLKs, then the part will enter
Power-Down and the conversion that was intiated by the
falling edge of CS will be terminated and SDATA will go
back into three-state. If CS is brought high before the
second SCLK falling edge, then the part will remain in
Normal Mode and will not power-down. This will avoid
accidental power-down due to glitches on the CS line.
SDATA
AD7276/AD7277/AD7278
SCLK
&6
A
1
SDATA
THE PART BEGINS
SCLK
TO POWER UP
&6
INVALID DATA
1
PRELIMINARY TECHNICAL DATA
10
2
Figure 13. Entering Power Down Mode
INVALID DATA
Figure 14. Exiting Power Down Mode
16
–16–
10
In order to exit this mode of operation and power the
AD7276/AD7277/AD7278 up again, a dummy conversion
is performed. On the falling edge of CS the device will
begin to power up, and will continue to power up as long
as CS is held low until after the falling edge of the 10th
SCLK. The device will be fully powered up once 16
SCLKs have elapsed and valid data will result from the
next conversion as shown in Figure 14. If CS is brought
high before the 10th falling edge of SCLK, then the
AD7276/AD7277/AD7278 will go back into Power-
Down again. This avoids accidental power up due to
glitches on the CS line or an inadvertent burst of 8 SCLK
cycles while CS is low. So, although the device may begin
to power up on the falling edge of CS, it will power down
again on the rising edge of CS as long as it occurs before
the 10th SCLK falling edge.
THREE-STATE
1
Preliminary Technical Data
POWERED UP WITH V IN
THE PART IS FULLY
16
FULLY ACQUIRED
VALID DATA
16
REV. PrF