CS5155GD16 CHERRY [Cherry Semiconductor Corporation], CS5155GD16 Datasheet - Page 5

• Manufacturer Part Number: CS5155GD16
• Description: CPU 5-Bit Synchronous Buck Controller
• Manufacturer: CHERRY [Cherry Semiconductor Corporation]

COMP
16L SO Narrow & PDIP
V
LGnd
V
CC1
V
V
V
V
V
V
FFB
SS
ID0
ID1
ID2
ID3
ID4
FB
PACKAGE PIN #
10
11
12
13
14
15
16
Slow Feedback
Fast Feedback
7
8
9
3.90V
3.85V
+
5 BIT
DAC
-
V
Comparator
CC1
Monitor
+
-
Error
Amplifier
PIN SYMBOL
1V
V
V
COMP
PGnd
LGnd
GATE(H)
GATE(L)
C
V
V
V
V
OFF
CC2
CC1
FFB
FB
PWM
Comparator
+
+
-
-
V
Comparator
60mA
FFB
2mA
PWM
COMP
Package Pin Description: continued
Low
5V
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connect-
ed to the regulator output. The inner feedback loop terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5A peak switching current. Internal
circuit prevents V
taneously.
High current ground for the IC. The MOSFET drivers are referenced to
this pin. Input capacitor ground and the source of lower FET should be
tied to this pin.
Low FET driver pin capable of 1.5A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage feedback
which sets the output voltage. This pin can be connected directly to the
output or a remote sense trace.
2.5V
Block Diagram
0.7V
5
Maximum
Extended
On-Time
Off-Time
Off-Time
Timeout
Timeout
Timeout
Normal
+
-
+
-
SS High
Comparator
SS Low
Comparator
GATE(H)
Time Out
(30ms)
Timer
and V
FUNCTION
R
S
Off-Time
Timeout
FAULT
Latch
GATE(L)
Q
Q
R
S
FAULT
FAULT
PWM
Latch
from being in high state simul-
Edge Triggered
Q
Q
R
S
GATE(H) = OFF
One Shot
GATE(H) = ON
C
OFF
Q
V
CC1
PGnd
V
V
PGnd
V
C
GATE(L)
CC2
GATE(H)
OFF