TDA9550 PHILIPS [NXP Semiconductors], TDA9550 Datasheet - Page 37

• Manufacturer Part Number: TDA9550
• Description: TV signal processor-Teletext decoder with embedded m-Controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
The following software sequence should be used when
utilizing this mode for Power-Down or Idle:-
1. Disable INT1 using the IE SFR.
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the D/A Converter digital input level to the desired
4. Enter DC Compare mode by setting the ’DC_COMP’
5. Enable INT1 using the IE SFR.
6. Enter Power-Down/Idle. Upon wake-up the SAD
I2C Serial I/O Bus
The I
clock line (SCL). The definition of the I
found in the 80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
The device operates in four modes: -
The micro-controller peripheral is controlled by the Serial
Control SFR (S1CON) and its Status is indicated by the
status SFR (S1STA). Information is transmitted/received
to/from the I
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
The byte level I
port on the 8xC558, except for the clock rate selection bits
CR<2:0>. The operation of the subsystem is described in
detail in the 8xC558 datasheet and can be found in the
80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
Three different IIC selection tables for CR<2:0> can be
configured using the ROMBANK SFR (IIC_LUT<1:0>) as
follows: -
2000 Jun 22
Master Transmitter
Master Receiver
Slave Transmitter
Slave Receiver
TV signal processor-Teletext decoder with
embedded -Controller
threshold level using the SAD/SADB SFRs and select
the required input pin (P3.0, P3.1, P3.2 or P3,3) using
CH1, CH0 in the SAD SFR.
enable bit in the SADB SFR.
should be restored to its conventional operating mode
by disabling the ’DC_COMP’ control bit.
2
C bus consists of a serial data line (SDA) and a serial
2
C bus using the Data SFR (S1DAT) and the
2
C serial port is identical to the I
2
C protocol can be
2
C serial
37
‘558 nominal mode’ (iic_lut=”00”)
This option accommodates the 558 I2C. The various serial
rates are shown below: -
Table 7 IIC Serial Rates ‘558 nominal mode’
‘558 fast mode’ (iic_lut=”01”)
This option accommodates the 558 I
shown below: -
‘558 slow mode’ (iic_lut=”10”)
This option accommodates the 558 I
as shown below: -
Table 8 IIC Serial Rates ‘558 fast mode’
Table 9 IIC Serial Rates ‘558 slow mode’
CR2
CR2
CR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
CR1
TDA955X/6X/8X PS/N1 series
CR1
CR1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
CR0
CR0
CR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
f
divided by
clk
f
f
divided by
divided by
clk
clk
1600
3200
Tentative Device Specification
(6MHz)
240
160
120
60
40
30
1600
3200
6400
(6MHz)
(6MHz)
800
120
120
480
30
20
15
80
60
80
60
2
2
C rates divided by 2
C doubled rates as
I2C Bit Frequency
I2C Bit Frequency
I2C Bit Frequency
(KHz) at f
(KHz) at f
1.875
3.75
37.5
100
150
200
0.9375
25
50
(KHz) at f
1.875
3.75
12.5
200
300
400
100
100
7.5
50
75
50
75
clk
clk
clk