PCA9541ABS/01 NXP [NXP Semiconductors], PCA9541ABS/01 Datasheet - Page 12
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PCA9541ABS/01
Manufacturer Part Number
PCA9541ABS/01
Description
2-to-1 I2C-bus master selector with interrupt logic and reset
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCA9541ABS01.pdf
(41 pages)
NXP Semiconductors
PCA9541A_3
Product data sheet
Table 9.
As a master reads its Control Register
[1]
Table 10.
[1]
Switch to the new channel is done when the master initiating the switch request sends a
STOP command to the PCA9541A.
If either master wants to change the connection of the downstream channel, it needs to
write to its Control Register (Reg#01), and then send a STOP command because an
update of the connection to the downstream according to the values in the two internal
Control Registers happens only on a STOP command. Writing to one control register
followed by a STOP condition on the other master's channel will not cause an update to
the downstream connection.
When both masters request a switch to their own channel at the same time, the master
who last wrote to its Control Register before the PCA9541A receives a STOP command
wins the switching sequence. There is no arbitration performed.
The Auto Increment feature (AI = 1) allows to program the PCA9541A in 4 bytes:
Start
111A3A2A1A0 + 0
00010000
Data Reg#00
Data Reg#01
Stop
NMYBUS
0
1
0
1
NBUSON
0
1
0
1
MYBUS and NMYBUS is an exclusive-OR type function where:
Equal values (00b or 11b) means that the master reading its Control Register has control of the bus.
Different values (01b or 10b) means that the master reading its Control Register does not have control of
the bus.
BUSON and NBUSON is an exclusive-OR type function where:
Equal values (00b or 11b) means that the connection between the upstream and the downstream channels
is off.
Different values (01b or 10b) means that the connection between the upstream and the downstream
channels is on.
[1]
[1]
MYBUS and NMYBUS truth table
BUSON and NBUSON truth table
MYBUS
0
0
1
1
BUSON
0
0
1
1
[1]
[1]
PCA9541 Address + Write
Select Reg#00 with AI = 1
Interrupt Enable Register data
Control Register data
Rev. 03 — 16 July 2009
Slave channel
The master reading this combination has control of the bus.
The master reading this combination does not have control of the bus.
The master reading this combination does not have control of the bus.
The master reading this combination has control of the bus.
Slave channel
off
on
on
off
2-to-1 I
2
C-bus master selector with interrupt logic and reset
PCA9541A
© NXP B.V. 2009. All rights reserved.
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