PCA9542PWDH PHILIPS [NXP Semiconductors], PCA9542PWDH Datasheet - Page 6

• Manufacturer Part Number: PCA9542PWDH
• Description: 2-channel I2C multiplexer and interrupt controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
1999 Oct 07
2-channel I
BY TRANSMITTER
1
DATA OUTPUT
Figure 5. Slave address
SDA
SDA
2
SCL
DATA OUTPUT
BY RECEIVER
1
C multiplexer and interrupt controller
fixed
SCL FROM
SDA
MASTER
1
slave address
start condition
S
0
start condition
hardware selectable
S
1
START condition
A2
1
1
X
1
2
A1 A0
SLAVE ADDRESS
S
1
X
1
3
SLAVE ADDRESS
1
X
0
4
Figure 4. Acknowledgement on the I
0
A2
X
5
A2
A1
X
Figure 6. WRITE control register
Figure 7. READ control register
1
6
A1
SW00453
A0
X
7
A0
R/W
X
0
8
R/W
1
A
X
acknowledge
from slave
9
2
A
acknowledge
from slave
X
X
6
1
X
X
X
PREVIOUS CHANNEL
2
CONTROL REGISTER
INT1
X
CONTROL REGISTER
not acknowledge
X
INT1
3
INT0
acknowledge
X
4
INT0
8
X
X
5
2
X
C-bus
B2
X
6
B2
acknowledge
from slave
B1
no acknowledge
from master
X
7
B1
B0
X
9
8
B0
A
last byte
t
pv
9
NA
P
P
stop condition
clock pulse for
acknowledgement
SW00481
NEW CHANNEL
SW00480
Product specification
PCA9542
SW00368