PCA9575HF NXP [NXP Semiconductors], PCA9575HF Datasheet

PCA9575HF

Manufacturer Part Number

PCA9575HF

Description

16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.PCA9575HF.pdf (38 pages)

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1. General description

The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel

Input/Output (GPIO) expansion in low voltage processor and handheld battery powered

mobile applications and was developed to enhance the NXP family of I

expanders. The improvements include lower supply current, lower operating voltage of

1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between

1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports

can be conﬁgured as an input or output independent of each other and default on start-up

to inputs.

I/O expanders provide a simple solution when additional I/Os are needed while keeping

interconnections to a minimum; for example in battery powered mobile applications and

clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to

providing a ﬂexible set of GPIOs, it simpliﬁes interconnection of a processor running at

one voltage level to I/O devices operating at a different (usually higher) voltage level.

PCA9575 has built-in level shifting feature that makes these devices extremely ﬂexible in

mixed signal environments where communication between incompatible I/Os is required.

The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can

operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or

pull-down feature for I/Os is also provided.

The output stage consists of two banks each of 8-bit conﬁguration registers, input

registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down

registers and polarity inversion registers. These registers allow the system master to

program and conﬁgure 16 GPIOs through the I

The system master can enable the I/Os as either inputs or outputs by writing to the I/O

conﬁguration register bits. The data for each input or output is kept in the corresponding

Input or Output register. The polarity of the read registers can be inverted with the Polarity

Inversion register (active HIGH or active LOW operation). Either a bus-hold function or

pull-up/pull-down feature can be selected by programming corresponding registers. The

bus-hold provides a valid logic level when the I/O bus is not actively driven. When

bus-hold feature is not selected, the I/O ports can be conﬁgured to have pull-up or

pull-down by programming the pull-up/pull-down conﬁguration register.

An open-drain interrupt output pin (INT) allows monitoring of the input pins and is

asserted each time a change occurs on an input port unless that port is masked

(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s

at the same time even if they have different individual I

optimal code programming when more than one device needs to be programmed with the

same instruction or if all outputs need to be turned on or off at the same time. The internal

PCA9575

16-bit I

with reset and interrupt

Rev. 03 — 9 November 2009

C-bus and SMBus, level translating, low voltage GPIO

C-bus.

C-bus addresses. This allows

Product data sheet

C-bus I/O

Related parts for PCA9575HF

PCA9575HF Summary of contents

Page 1

PCA9575 16-bit I with reset and interrupt Rev. 03 — 9 November 2009 1. General description The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery ...

Page 2

NXP Semiconductors Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O banks are held in its default ...

Page 3

... I Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9575PW2 PCA9575PW2 PCA9575PW1 PA9575PW1 PCA9575HF 575F PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO Package Name Description TSSOP28 plastic thin shrink small outline package; 28 leads; ...

Page 4

NXP Semiconductors 5. Block diagram SCL SDA V DD RESET V SS (1) PCA9575PW2 only. Fig 1. PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO PCA9575 2 I ...

Page 5

NXP Semiconductors data from shift register configuration register data from D Q shift register FF write configuration CK Q pulse write pulse read pulse BUS-HOLD AND PULL-UP/PULL-DOWN CONTROL data from shift register write polarity pulse Fig 2. Simpliﬁed schematic of ...

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... P1_1 20 P1_2 19 P1_3 18 V DD(IO)1 17 P1_4 16 P1_5 15 P1_6 14 P1_7 002aad564 Fig 4. terminal 1 index area P0_1 1 P0_2 2 3 P0_3 PCA9575HF V 4 DD(IO)0 P0_4 5 6 P0_5 Transparent top view Rev. 03 — 9 November 2009 PCA9575 RESET P0_0 4 25 P0_1 ...

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NXP Semiconductors 6.2 Pin description Table 2. Symbol RESET P0_0 P0_1 P0_2 P0_3 A1 V DD(IO)0 P0_4 P0_5 P0_6 P0_7 INT P1_7 P1_6 P1_5 P1_4 V DD(IO)1 A3 P1_3 P1_2 P1_1 P1_0 SDA SCL ...

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NXP Semiconductors 7. Functional description 7.1 I/O ports The 16 I/O ports are organized as two banks of 8 ports each. The system master can enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration register ...

Page 9

NXP Semiconductors 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9575, which will be stored in the Command register. Fig 8. The lowest 4 bits ...

Page 10

NXP Semiconductors Table 3. Register summary …continued Register number D3 D2 0Dh 1 1 0Eh 1 1 0Fh 1 1 7.5 Writing to port registers Data is transmitted to the PCA9575 by sending the device address and setting the least ...

Page 11

NXP Semiconductors 7.6.2 Register 1 - Input port 1 register This register is read-only. It reﬂects the incoming logic levels of the pins, regardless of whether the pin is deﬁned as an input or an output by the Conﬁguration register. ...

Page 12

NXP Semiconductors 7.6.4 Register 3 - Polarity inversion port 1 register This register allows the user to invert the polarity of the Input port register data bit in this register is set (written with ‘1’), the corresponding Input ...

Page 13

NXP Semiconductors 7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O ...

Page 14

NXP Semiconductors 7.6.7 Register 6 - Pull-up/pull-down select port 0 register When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O port 0 can be conﬁgured to have pull-up or pull-down ...

Page 15

NXP Semiconductors 7.6.9 Register 8 - Conﬁguration port 0 register This register conﬁgures the direction of the I/O pins bit in this register is set (written with logic 1), the corresponding port 0 pin is enabled as an ...

Page 16

NXP Semiconductors 7.6.11 Register 10 - Output port 0 register This register is an output-only port. It reﬂects the outgoing logic levels of the pins deﬁned as outputs by Register 8. Bit values in this register have no effect on ...

Page 17

NXP Semiconductors 7.6.13 Register 12 - Interrupt mask port 0 register All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding ...

Page 18

NXP Semiconductors 7.6.15 Register 14 - Interrupt status port 0 register This register is read-only used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros. Table 18. Legend: * ...

Page 19

NXP Semiconductors 7.9 Software reset The Software Reset Call allows all the devices in the I state value through a speciﬁc formatted I implies that the I The Software Reset sequence is deﬁned as following START command is ...

Page 20

NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

Page 21

NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 11. System conﬁguration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed ...

Page 22

NXP Semiconductors 9. Bus transactions Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see and Figure Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 16). SCL ...

Page 23

NXP Semiconductors (1) slave address SDA START condition acknowledge from slave (1) slave address (cont (repeated) START condition (1) Slave address shown in this example is for ...

Page 24

NXP Semiconductors 10. Application design-in information 3.6 V 1 MASTER CONTROLLER SCL SDA INT RESET V SS Address pin connections shown are for the 28-pin version. Device address conﬁgured ...

Page 25

NXP Semiconductors 12. Static characteristics Table 21. Static characteristics DD(IO)0 otherwise speciﬁed. Symbol Parameter Supplies V supply voltage DD V input/output supply voltage 0 ...

Page 26

NXP Semiconductors Table 21. Static characteristics DD(IO)0 otherwise speciﬁed. Symbol Parameter Interrupt INT I LOW-level output current OL Select inputs (reset and address) V ...

Page 27

NXP Semiconductors (mA amb + 0.2 0 1.8 V DD(IO)0 DD(IO)1 Fig 21. I versus 13. Dynamic characteristics ...

Page 28

NXP Semiconductors Table 22. Dynamic characteristics DD(IO)0 otherwise speciﬁed. Symbol Parameter Port timing t data output valid time v(Q) t data input set-up time ...

Page 29

NXP Semiconductors SCL SDA RESET rec(rst) P0_0 to P0_7 P1_0 to P1_7 Fig 23. Reset timing 14. Test information R = load resistance load capacitance includes jig and probe capacitance termination ...

Page 30

NXP Semiconductors 15. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. ...

Page 31

NXP Semiconductors TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 32

NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS ...

Page 33

NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages ...

Page 34

NXP Semiconductors • Process issues, such as application of adhesive and ﬂux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath speciﬁcations, including temperature and impurities ...

Page 35

NXP Semiconductors Fig 28. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 18. Abbreviations Table 25. Acronym CBT CDM CMOS DUT ESD GPIO HBM ...

Page 36

NXP Semiconductors 19. Revision history Table 26. Revision history Document ID Release date PCA9575_3 20091109 • Modiﬁcations: Added Figure 20 “I • Added Figure 21 “I PCA9575_2 20090727 PCA9575_1 20081002 PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, ...

Page 37

NXP Semiconductors 20. Legal information 20.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 38

NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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