AD5113 AD [Analog Devices], AD5113 Datasheet - Page 15

• Manufacturer Part Number: AD5113
• Manufacturer: AD [Analog Devices]

Data Sheet
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input
voltage at A to B, as shown in Figure 43. Unlike the polarity of
V
to-A, and W-to-B can be at either polarity.
If ignoring the effect of the wiper resistance for simplicity,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at V
input voltage applied to Terminal A and Terminal B, is:
where:
R
R
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the internal resistors, R
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The
protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed V
clamped by the forward-biased diode. There is no polarity
constraint between V
than V
POWER-UP SEQUENCE
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
Figure 44), it is important to power on V
WB
AW
DD
(D) can be obtained from Equation 1 or Equation 2.
(D) can be obtained from Equation 3 to Equation 5 .
to GND, which must be positive, voltage across A-to-B, W-
AD5116
V
W
DD
(
D
or lower than GND.
)

Figure 43. Potentiometer Mode Configuration
is designed with internal ESD diodes for
R
WB
R
AB
(
W
D
, with respect to ground for any valid
)
A
V
, V

IN
V
W
A
, and V

A
B
R
AW
R
W
AB
B
(
, but they cannot be higher
D
)
V
WA

OUT
V
DD
and R
B
before applying
WB
, and not the
DD
are
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any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that V
powered on unintentionally and can affect other parts of the
circuit. Similarly, V
power-on sequence is in the following order: GND, V
V
important as long as they are powered on after V
states of the PU and PD pins can be logic low or floating,
but they should not be logic high during power-on.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 45 illustrates the basic supply bypassing config-
uration for the AD5116.
A
/V
B
/V
Figure 44. Maximum Terminal Voltages Set by V
W
. The order of powering V
V
DD
10µF
Figure 45. Power Supply Bypassing
C2
DD
+
should be powered down last. The ideal
C1
0.1µF
A
, V
V
AD5116
DD
B
GND
, and V
AGND
V
A
W
B
GND
DD
DD
W
DD
and V
is not
. The
AD5116
DD
DD
SS
, and
is