PCA9663B NXP [NXP Semiconductors], PCA9663B Datasheet
PCA9663B
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PCA9663B Summary of contents
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PCA9663 Parallel bus to 3 channel Fm+ I Rev. 1 — 6 June 2011 1. General description The PCA9663 is an advanced single master mode I generation bus controller designed for data intensive I independent I (Fm+) open-drain topology. Each ...
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... Entertainment systems LED matrix control Data intensive I 4. Ordering information Table 1. Type number PCA9663B PCA9663 Product data sheet Parallel bus to 3 channel Fm C-bus capable and compatible with SMBus 2 C-bus port to controllers/processors that do not have one 2 C-bus ports to controllers/processors that need multiple I ...
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NXP Semiconductors 5. Block diagram SDA0 SCL0 SDA1 SCL1 SDA2 SCL2 V DD(IO) Fig 1. PCA9663 Product data sheet Parallel bus to 3 channel Fm+ I Channel 0 2 Fm+ I C-bus control STATUS0_[n] CONTROL CHSTATUS INTMSK SLATABLE TRANCONFIG DATA ...
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... PCA9663 Product data sheet Parallel bus to 3 channel Fm PCA9663B Pin configuration for LQFP48 Pin description Pin Type Description 3 I Address inputs: selects the bus controller’s internal registers and ports for read/write operations ...
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NXP Semiconductors Table 2. Symbol TRST TMS TCK TDI TDO INT SDA2 SCL2 SDA1 SCL1 SDA0 SCL0 TRIG RESET V DD(IO) V SS(IO) PCA9663 Product data sheet Parallel bus to 3 channel Fm+ I Pin description …continued ...
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NXP Semiconductors Table 2. Symbol Functional description 7.1 General The PCA9663 acts as an interface device between standard high-speed parallel buses and the serial C-bus and the parallel-bus host is carried out ...
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NXP Semiconductors DATA until the entire sequence is loaded. If the transaction is a read transaction, the host must write a dummy byte (i.e., FFh) for each expected serial read byte to reserve the memory space in the buffer for ...
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NXP Semiconductors Remark: Note that the bytes required to store the 30 slave addresses are not included in the calculation since they are stored in the SLATABLE register. 7.4 Error reporting and handling In case of any transaction error conditions, ...
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Table 3. PCA9663 register address map - direct register access Register name Access Channel status registers 0 0 channel 0 transaction number STATUS0_[n] (hex channel 1 transaction number STATUS1_[n] (hex) ...
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Table 3. PCA9663 register address map - direct register access Register name Access Channel 1 (Fm+) registers CONTROL CHSTATUS 0 ...
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Table 3. PCA9663 register address map - direct register access Register name Access Channel 2 (Fm+) registers CONTROL CHSTATUS 0 ...
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Table 3. PCA9663 register address map - direct register access Register name Access Global registers CTRLSTATUS CTRLINTMSK ...
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NXP Semiconductors 7.5.1 Channel registers 7.5.1.1 STATUS0_[n], STATUS1_[n], STATUS2_[n] — Transaction status registers STATUS0_[n], STATUS1_[n], and STATUS2_[n] are 8-bit 64 read-only registers that provide status information for a given transaction. Only the 5 lower bits are used; the top ...
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NXP Semiconductors After STA is set: STATUSx_[ STATUSx_[ STATUSx_[ STATUSx_[ Since there is no timing requirement in setting the STA bit after the initialization, the device will update the first status ...
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NXP Semiconductors Table 5. CONTROL - Control register bit description Address: Channel 0 = C0h; Channel 1 = D0h; Channel 2 = E0h. Legend: * reset value Bit Symbol Access Value R/W 1 ...
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NXP Semiconductors Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior Channel state (initialization steps) Idle (reset, TRANCONFIG, SLATABLE, DATA, STA = 0) Active (reset, load TRANCONFIG, SLATABLE, DATA, STA = 1 REFRATE Loop idle (reset, load TRANCONFIG, [1] SLATABLE, ...
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NXP Semiconductors Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior Channel state (initialization steps) Trigger Loop active (reset, load TRANCONFIG, SLATABLE, DATA, STA = 1) [1] Loop Idle is defined as the time elapsed from a STOP to the ...
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NXP Semiconductors FE - Frame Error bit: exceeds the refresh rate programmed in the REFRATE register or the time between trigger ticks. Solving frame errors include programming longer refresh rates, speeding up the bus frequency, shortening the amount of bytes ...
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NXP Semiconductors Table 8. Error detection operation/behavior Channel state AR (MODE register) Active or idle X Active or idle, time-out X enabled, and clock line is LOW Active and at a START or 1 repeated-START condition 1 0 7.5.1.4 INTMSK ...
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NXP Semiconductors 7.5.1.5 SLATABLE — Slave address table register SLATABLE is an 8-bit 64 register set that makes up a table that stores the slave address for each transaction in the sequence. The table is loaded by using an ...
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NXP Semiconductors 7.5.1.6 TRANCONFIG — Transaction configuration register The TRANCONFIG register is an 8-bit 65 register set that makes up a table that contains the number of transactions that will be executed in a sequence and the number of ...
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NXP Semiconductors To return to the data location pointed by the contents of the TRANSEL and TRANOFS register after read or write access to the DATA register, set the AIPTRRST (auto-increment pointer reset) bit in the control register. To return ...
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NXP Semiconductors 7.5.1.9 TRANOFS — Transaction data buffer byte select register In conjunction with the TRANSEL register, the TRANOFS register is used to select the pointer to a specific byte in a transaction in the data buffer. This allows the ...
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NXP Semiconductors If the FRAMECNT is 01h defined as the default state and the sequence stored in the buffer will be sent once and a STOP will be sent at the end of the sequence. If the FRAMECNT ...
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NXP Semiconductors The clock is derived from the internal PLL frequency which is set at 156 MHz (13 OSC clock). Given accuracy on the internal clock, the worst case T --------------------------------------- - 12.12 MHz Calculating clock settings ...
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NXP Semiconductors Table 24. Data shown under following conditions: Pull-up resistor R Desired frequency (kHz) Fast-mode (Fm) 400 350 300 250 200 150 100 Fast-mode Plus (Fm+) 1000 900 800 700 600 500 400 Remark: The correct MODE setting should ...
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NXP Semiconductors 7.5.1.14 MODE — I MODE is a read/write register. It contains the control bits that select the bus recovery options, and the correct timing parameters. Timing parameters involved with AC[1:0] are BUF HD;STA contained in ...
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NXP Semiconductors Table 26. SCLL (decimal) 118 [1] SCLL and SCLH values in the table also represents the minimum values that can be used for the corresponding I [2] Using the formula 7.5.1.15 TIMEOUT — Time-out register ...
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NXP Semiconductors 7.5.1.16 PRESET — I Table 28. Address: Channel 0 = CFh; Channel 1 = DFh; Channel 2 = EFh. Bit 7:0 PRESET is an 8-bit write-only register. Programming the PRESET register allows the user to reset each individual ...
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NXP Semiconductors The buffer error may occur when a data location is being read or written to that has not previously been configured by the TRANCONFIG register. The buffer error can occur on a parallel data write or read beyond ...
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NXP Semiconductors 7.5.2.2 CTRLINTMSK — Control Interrupt mask register The CTRLINTMSK masks all interrupts generated by the masked channel. This allows the host MCU to complete other operations before servicing the interrupt without being interrupted by the same channel. Table ...
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NXP Semiconductors sources and masks sources and masks sources and masks Fig 5. 7.5.2.3 DEVICE_ID — Device ID The DEVICE_ID register stores the bus controller part number so it can be identified on the parallel bus. Table 31. Address: F6h. ...
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NXP Semiconductors 7.5.2.4 CTRLPRESET — Parallel software reset register Table 32. Address: F7h. Bit 7:0 CTRLPRESET is an 8-bit write-only register. Programming the CTRLPRESET register allows the user to reset the PCA9663 under software control. The software reset is achieved ...
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NXP Semiconductors ADDR CE RD DATA Fig 7. ADDR CE WR DATA Fig 8. 8. PCA9663 operation The PCA9663 is designed to efficiently transmit and receive large amounts of data on a single master bus. There are three major components ...
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NXP Semiconductors Transmitter or a Master Receiver according to the direction bits specified in the SLATABLE. The host has the ability to retrieve stored serial data as soon as a read transaction is done, while the controller carries on the ...
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NXP Semiconductors When the interrupts are unmasked, a NACK on slave address or data (in a write cycle) will terminate the serial transfer, generate a STOP, and the INT pin will be asserted. The host can read the CTRLSTATUS (Controller ...
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WEMSK and REMSK = 0 S SLA DATA A S SLA 01h 01h 08h 04h 20h 20h transactions with WEMSK and REMSK = 1 S SLA DATA ...
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SLATABLE - 00h 10h SLAW 00h 01h 11h SLAR 01h 02h 40h SLAW 02h 03h E0h SLAW 03h : : : : 3Dh 20h SLAW 3Dh 3Eh 33h SLAR 3Eh ...
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NXP Semiconductors 8.2 Read transactions 2 Many I In this case, a read transaction is actually a multi-part transaction consisting of a write transaction followed by a read transaction. This is done by setting the transactions in that order when ...
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NXP Semiconductors Once the FRAMECNT values is reached, the FLD bit in the CHSTATUS register is set and no further transactions will be executed and the channel will go to the idle state. The FLD interrupt can be masked with ...
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NXP Semiconductors 8.5 Bus errors Bus errors are a rare occurrence in a well designed I robust error detection mechanism that detects hang-ups such as if SDA or SCL is pulled LOW by an external source illegal ...
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NXP Semiconductors SDA line SCL line Fig 11. Recovering from a bus obstruction caused by a LOW level on SDA ( 8.5.2 I C-bus obstructed by a LOW level on SCL (CLE C-bus hang-up ...
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NXP Semiconductors 8.6 Power-on reset When power is applied to V condition until V PCA9663 goes to the power-up initialization phase where the following operations are performed: 1. The oscillator and PLL will be re-initialized. 2. Internal register initialization is ...
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NXP Semiconductors 8.8 Channel reset In addition to the above chip reset options, each channel can be individually reset by programming the PRESET register for that channel as described in channel will reset to its default power-up state. The host ...
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NXP Semiconductors 2 8.9 I C-bus timing diagrams The diagrams SCL SDA condition (1) 7-bit address + R byte and number of bytes sent = value programmed in Transaction length Fig 14. Bus timing diagram; write transactions SCL ...
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NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...
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NXP Semiconductors SDA SCL PCA9663 MASTER TRANSMITTER/ RECEIVER Fig 18. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is ...
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NXP Semiconductors 10. JTAG port The PCA9663 has a JTAG IEEE 1149.1 compliant port. All signals (TDI, TMS, TCK, TRSTN and TDO) are accessible. Only EXTEST functions are enabled, for example to conduct board-level continuity tests. Device debug/emulation functionality such ...
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NXP Semiconductors 11. Application design-in information V DD address bus 80C51 DECODER ALE V SS Fig 20. Application diagram using the 80C51 11.1 Specific applications The PCA9663 is a parallel bus to I devices to interface with I not have ...
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NXP Semiconductors 2 11.2 Add I As shown in capable I that need to interface with I Fig 21. Adding I 11.3 Add additional I The PCA9663 can be used to convert 8-bit parallel data into additional single master capable ...
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NXP Semiconductors 12. Limiting values Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input/output supply voltage DD(IO) V input voltage I I input current I I output ...
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NXP Semiconductors Table 35. Static characteristics 3 3 amb Symbol Parameter Inputs WR, RD A7, CE, TRIG V LOW-level input voltage IL V HIGH-level input voltage IH V ...
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NXP Semiconductors 14. Dynamic characteristics Table 36. Dynamic characteristics (3.3 volt) 3 amb Symbol Parameter Initialization timing t power-on initialization time init(po) t initialization time init RESET timing ...
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NXP Semiconductors (read) Fig 23. Bus timing (read cycle (write) Fig 24. Parallel bus timing (write cycle) PCA9663 Product data sheet Parallel bus to 3 channel Fm+ I ...
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NXP Semiconductors Fig 25. Data timing PCA9663 Product data sheet Parallel bus to 3 channel Fm RD, CE input d(QLZ output LOW-to-float float-to-LOW d(QHZ ...
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Table 37. I C-bus frequency and timing specifications All the timing limits are valid within the operating supply voltage and ambient temperature range; V and refer to V and V with an input voltage ...
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NXP Semiconductors SDA t LOW t f SCL t HD;STA S Fig 26. Definition of timing on the I START protocol condition ( SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer ...
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NXP Semiconductors 15. Test information Fig 28. Test circuitry for switching times Table 38. Test d(DV) d(QZ) Fig 29. Test circuitry for open-drain switching times Table 39. Test t as(int) t das(int) PCA9663 Product data sheet Parallel ...
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NXP Semiconductors 16. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...
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NXP Semiconductors 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages ...
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NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities ...
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NXP Semiconductors Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 42. Acronym ASIC CPU CDM DSP ESD Fm+ HBM 2 ...
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NXP Semiconductors 21. Legal information 21.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use neither qualified nor tested in accordance with automotive testing ...
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NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...
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NXP Semiconductors 22 Contact information Contents . . . . . . . . . . . . ...