ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 10

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

ADV7340/ADV7341
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 13:
•
•
•
•
t
t
t
t
9
10
11
12
CONTROL
= Clock high time
= Clock low time
= Data setup time
= Data hold time
INPUTS
CONTROL
*SELECTED BY SUBADDRESS 0x01, BIT 7.
INPUTS
*SELECTED BY SUBADDRESS 0x01, BIT 7.
S_HSYNC,
S_VSYNC
CONTROL
C9 TO C0*
Y9 TO Y0*
OUTPUTS
S9 TO S0/
Y9 TO Y0/
CLKIN_A
CONTROL
S_HSYNC,
S_VSYNC
Y9 TO Y0*
OUTPUTS
S9 TO S0/
CLKIN_A
Figure 3. SD Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
t
Figure 2. SD Only, 8-/10-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
Cb0
9
t
9
Cb0
Y0
t
10
t
10
t
11
Y0
t
11
Cr0
t
12
t
12
Cr0
Y1
Rev. 0 | Page 10 of 88
Y1
Cb2
t
14
t
t
In addition, refer to Table 31 for the ADV7340/ADV7341 input
configuration.
t
14
13
13
Cb2
Y2
•
•
Y2
t
t
13
14
= Control output access time
= Control output hold time
Cr2
Cr2
Y3
IN SLAVE MODE
IN MASTER/SLAVE MODE
IN SLAVE MODE
IN MASTER/SLAVE MODE