PCA9691BS NXP [NXP Semiconductors], PCA9691BS Datasheet - Page 10

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PCA9691BS

Manufacturer Part Number
PCA9691BS
Description
8-bit A/D and D/A converter
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PCA9691_2
Product data sheet
Fig 9.
protocol
V
AOUT
SDA
SCL
D/A conversion sequence
S
7.3.1 Worst case example
1
ADDRESS
An example of the worst case is shown in
between 8T
When the I
9 μs.
The previous AOUT value is valid at least until the rising edge of the acknowledge bit
(8T
The latest start time of the new value is 5.6 μs from the rising edge of the acknowledge bit:
(18T
Fig 8.
2
previous value held in DAC register
osc
osc
≥ 1.23 μs).
high-impedance state of
≤ 5.6 μs) so AOUT is stable after t
DAC data and DC conversion characteristics
0
8
2
osc
C-bus is driven at 1 MHz (full speed) then the DAC is operating at a rate of
and 18T
A
9
V
CONTROL BYTE
AOUT
V
1
V
Rev. 02 — 27 January 2010
AGND
VREF
V
osc
V
DD
SS
.
00
V
MSB
01 02 03 04
AOUT
D7 D6 D5 D4 D3 D2 D1 D0
8
t
d
= V
A
9
AGND
t
s(DAC)
s(DAC)
Figure
+
DATA BYTE 1
1
V
VREF
previous value held
≤ 2.4 μs.
in DAC register
256
10. The delay time can have a value
− V
AGND
8
i = 0
Σ Di × 2
t
7
d
LSB
A
9
8-bit A/D and D/A converter
DAC data
register
i
DAC (hex)
001aag468
t
s(DAC)
FE FF
DATA BYTE 2
1
PCA9691
value of data byte 1
© NXP B.V. 2010. All rights reserved.
8
001aag469
A
time
9
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