X9440WP24 INTERSIL [Intersil Corporation], X9440WP24 Datasheet - Page 2
![no-image](/images/no-image-200.jpg)
X9440WP24
Manufacturer Part Number
X9440WP24
Description
Mixed Signal with SPI Interface
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.X9440WP24.pdf
(21 pages)
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9440.
Chip Select (CS)
When CS is HIGH, the X9440 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9440, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
Device Address (A
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9440. A maximum of 4 devices may share the
same SPI serial bus.
0
-A
1
)
2
X9440
Potentiometer Pins
V
The V
nections on either end of a mechanical potentiometer.
V
The wiper output V
of a mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input V
V
inverting) inputs of the two comparators.
Buffered Voltage Outputs V
V
outputs controlled by bits in the volatile analog control
register.
Hardware Write Protect Input WP
The WP pin when low prevents non volatile writes to
the wiper counter and analog control registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.
System Supply V
The system supply, V
to bias the interface and control circuits.
H
W
NI0
OUT0
(V
(V
and V
H0
H
W0
and V
-V
and V
-V
H3
W1
NI1
), V
OUT1
L
)
are the input voltages to the plus (non-
inputs are equivalent to the terminal con-
L
NI0
(V
are the buffered voltage comparator
CC
L0
, V
W
-V
and Ground V
is equivalent to the wiper output
CC
NI1
L3
and its reference V
)
OUT0
, V
SS
OUT1
SS
March 28, 2005
is used
FN8200.0