X9448WP24 INTERSIL [Intersil Corporation], X9448WP24 Datasheet - Page 5

• Manufacturer Part Number: X9448WP24
• Description: Mixed Signal with 2-Wire Interface
• Manufacturer: INTERSIL [Intersil Corporation]

or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
Counter Register current wiper position to a data reg-
ister is a write to nonvolatile memory and takes a mini-
mum of t
between one of the two potentiometers or one of the
two voltage comparators and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between both of the potentiometers and volt-
age comparators and one of their associated registers.
Four instructions require a three-byte sequence to com-
plete. The basic sequence is illustrated in Figure 4.
These instructions transfer data between the host and
the X9448; either between the host and one of the data
registers or directly between the host and the wiper
counter and analog control registers. These instructions
are: read wiper counter register or analog control regis-
ter, read the current wiper position of the selected pot or
Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
SCL
SDA
S
T
A
R
T
S
T
A
R
T
WR
0
SDA
SCL
0
to complete. The transfer can occur
1
1
STPWV
0
S
T
A
R
T
0
1
0
. A transfer from the Wiper
1
A3 A2 A1 A0 A
5
A3 A2 A1 A0
1
0
1
A3 A2 A1 A0
C
K
A
C
K
I3
I3
I2
I2
I1 I0
X9448
I1
A
C
K
P1 P0 R1 R0 A
I0
I3
the comparator control bits, Write wiper counter register
or analog control register, i.e. change current wiper
position of the selected pot or control the voltage com-
parator; read data register, read the contents of the
selected nonvolatile register; write data register, write a
new value to the selected data register. The bit struc-
tures of the instructions are shown in Figure 6.
The increment/decrement command is different from
the other commands. Once the command is issued
and the X9448 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
move one resistor segment towards the V
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V
sequence for this operation is shown in Figure 5.
P1 P0 R1 R0 A
HIGH
I2
) while SDA is HIGH, the selected wiper will
I1
X
I0
C
K
X
R1 R0 P1 P0
L
C
K
terminal. A detailed illustration of the
N
C
1
I
D5 D4 D3 D2 D1 D0
N
C
2
I
A
C
K
N
C
n
I
S
T
O
P
D
E
C
1
H
D
E
C
n
A
C
K
terminal.
April 18, 2005
O
S
T
P
S
T
O
P
FN8201.0