X9260 INTERSIL [Intersil Corporation], X9260 Datasheet - Page 7

• Manufacturer Part Number: X9260
• Description: Dual Supply/Low Power/256-Tap/SPI bus
• Manufacturer: INTERSIL [Intersil Corporation]

DEVICE DESCRIPTION
Instructions
I
The first byte sent to the X9260 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9260; this is fixed as
0101[B] (refer to Table 3).
The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9260
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9260 to successfully continue the
Table 3. Identification Byte Format
Table 4. Instruction Byte Format
DENTIFICATION
(MSB)
(MSB)
ID3
I3
0
ID2
I2
B
1
YTE
Device Type
Instruction
Opcode
Identifier
( ID
7
AND
ID1
I1
0
A )
I0
ID0
1
RB
A3
Selection
Register
X9260
Data
RA
command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V
I
The next byte sent to the X9260 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.
A2
NSTRUCTION
Slave Address
CC
0
A1
or V
B
YTE
(WCR Selection)
Pot Selection
SS
(LSB)
( I[3:0] )
.
(LSB)
P0
A0
February 28, 2005
FN8170.0