AD1937 AD [Analog Devices], AD1937 Datasheet
AD1937
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AD1937 Summary of contents
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... By using the on-board PLL to derive the master clock from the LR (frame) clock or from an external crystal, the AD1937 elimi- nates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architecture to further minimize EMI ...
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... AD1937 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Test Conditions ............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 5 Digital Specifications ................................................................... 6 Power Supply Specifications........................................................ 6 Digital Filters ................................................................................. 7 Timing Specifications .................................................................. 8 Timing Diagrams .......................................................................... 9 Absolute Maximum Ratings .......................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ...
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... kHz, −60 dB input 96 98 −1 dBFS −10 −0.25 −10 100 mV rms, 1 kHz 100 mV rms, 20 kHz All DACs kHz, −60 dB input 102 105 Rev Page AD1937 , 256 × f mode Typ Max Unit 24 Bits 102 dB 105 dB −96 − ...
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... AD1937 Parameter Total Harmonic Distortion + Noise Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage ...
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... kHz, −60 dB input 101 104 0 dBFS Two channels running Eight channels running −10 −0.2 −25 −30 FILTR pin FILTR pin 1.32 CM pin VSUPPLY pin 4.5 VSENSE pin 3.2 Min Typ 3.5 Rev Page AD1937 Typ Max Unit 24 Bits 102 dB 104 dB −96 −87 dB 1.9 V rms +10 % +0. +10 mV ...
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... AD1937 DIGITAL SPECIFICATIONS −40°C < T < +130°C, DVDD = 3.3 V ± 10%. A Table 5. Parameter INPUT High Level Input Voltage ( Low Level Input Voltage ( Input Leakage Input Capacitance OUTPUT High Level Output Voltage ( Low Level Output Voltage ( POWER SUPPLY SPECIFICATIONS Table 6 ...
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... S 0.5 × 0.5465 × 0.6354 × 0.6354 × f 122 ÷ f 521 S 11 ÷ f 115 S 8 ÷ AD1937 Max Unit kHz dB kHz kHz dB μs kHz kHz kHz ±0.01 dB ±0.05 dB ±0.1 dB kHz kHz kHz kHz kHz kHz μ ...
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... AD1937 TIMING SPECIFICATIONS −40°C < T < +130°C, DVDD = 3.3 V ± 10%. A Table 8. Parameter INPUT MASTER CLOCK (MCLK) AND RESET MCLK f MCLK t PDR t PDRR PLL Lock Time 256 f VCO Clock, Output Duty Cycle, S MCLKO/MCLKXO Pin SCL t SCLL t SCLH ...
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... S-JUSTIFIED MODE ASDATAx RIGHT-JUSTIFIED MODE MSB – DDS MSB t DDH t DDS MSB Figure 2. DAC Serial Timing MSB – ABDD MSB t ABDD Figure 3. ADC Serial Timing Rev Page DLH t DDS LSB t t DDH DDH t ALH MSB LSB AD1937 ...
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... AD1937 ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Bit Clock for DACs. Can be programmed as input or output in all modes. Frame Clock for DACs. Can be programmed as input or output in all modes. Rev Page AGND 48 FILTR 47 AGND 46 AVDD 45 AGND 44 DAC2RN 43 DAC2RP 42 DAC2LN 41 DAC2LP 40 DAC1RN 39 DAC1RP 38 DAC1LN 37 DAC1LP 36 ADDR1 35 SCL 34 DGND AD1937 ...
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... AD1937 1 Pin No. Type Mnemonic 23 I VSUPPLY 24 I VSENSE 25 O VDRIVE 26 I/O ASDATA2 27 O ASDATA1 28 I/O ABCLK 29 I/O ALRCLK 30 I ADDR0 31 I/O SDA 34 I SCL 35 I ADDR1 36 O DAC1LP 37 O DAC1LN 38 O DAC1RP 39 O DAC1RN 40 O DAC2LP 41 O DAC2LN 42 O DAC2RP 43 O DAC2RN 47 O FILTR 49, 50, 63, 64 ...
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... Rev Page – FREQUENCY (kHz) Figure 8. DAC Stop-Band Filter Response, 48 kHz FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 96 kHz 0 – FREQUENCY (kHz) Figure 10. DAC Stop-Band Filter Response, 96 kHz AD1937 ...
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... AD1937 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 11. DAC Pass-Band Filter Response, 192 kHz Rev Page –2 –4 –6 –8 – FREQUENCY (kHz) Figure 12. DAC Stop-Band Filter Response, 192 kHz 96 ...
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... In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if the AD1937 is programmed in 256 × f mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1937 is then switched to 96 kHz operation (by writing to the I master clock should remain at 12.288 MHz, which is 128 × ...
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... The device address consists of an internal built-in address (0x08) OR’ with the two address bits, ADDR1 and ADDR0, and the R/ W bit. The two address bits allow four AD1937s to be used in a system. Tie I program the ADDR bits accordingly Initiating a write operation to the AD1937 involves sending a start condition and then sending the device address with the R/ W bit set low ...
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... C Read Format Rev Page ACK. BY MASTER FRAME 2 REGISTER ADDRESS BYTE ACK. BY STOP BY MASTER (AM) MASTER (P) FRAME 3 DATA BYTE TO AD1937 ACK. BY AD1937 (AS) FRAME 2 REGISTER ADDRESS BYTE ACK. BY MASTER (AM) FRAME 4 REGISTER DATA ...
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... It is important that the analog supply be as clean as possible. The AD1937 includes a 3.3 V regulator driver that only requires an external pass transistor, a resistor, and bypass capacitors to turn supply into 3 the regulator driver is not used, connect VSUPPLY, VDRIVE, and VSENSE to DGND ...
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... RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LSB MSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL EXCEPT FOR DSP MODE, WHICH IS 2 × Figure 15. Stereo Modes Rev Page RIGHT CHANNEL LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB LSB LSB AD1937 ...
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... Combining the TDM/AUX ADC and DAC modes results in a system configuration of 8 ADCs and 12 DACs. The system, then consists of two external stereo ADCs, two external stereo DACs, and one AD1937. This mode is shown in Figure 21 (combined TDM/AUX DAC and ADC modes). In the TDM/AUX mode, the frame sync (ALRCLK) triggers ...
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... ADCL2 ADCR2 AUXL1 Figure 19. TDM/AUX Mode 8-Channel ADC Configuration Rev Page AUX DAC CHANNELS APPEAR AT AUX DAC PORTS DAC4L DAC4R AUX1L AUX1R AUX2L AUX2R RIGHT MSB MSB DACR3 DACL4 DACR4 4 AUX ADC CHANNELS AUXR1 AUXL2 AUXR2 RIGHT MSB MSB AD1937 ...
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... AD1937 ALRCLK ABCLK 4 ON-CHIP ADC CHANNELS ASDATA1 ADCL1 ADCR1 ADCL2 (TDM DATA OUT) MSB DLRCLK (AUX LRCLK IN/OUT) DBCLK (AUX BCLK IN/OUT) DSDATA2 (AUX ADC1 DATA IN) DSDATA3 (AUX ADC2 DATA IN) ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM DATA IN) ...
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... The I/O pins of the serial ports are defined according to the serial mode selected. See Table 19 for a detailed description of the function of each pin. See Figure 27 for a typical AD1937 configuration with two external stereo DACs and two external stereo ADCs. DAC2L ...
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... AD1937 AD1937 Figure 25. Single-Line Daisy-Chain TDM Mode 256 × f ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN ASDATA1 (TDM ADC DATA OUT) OF THE SECOND AD1937 ADCL1 ADCR1 IN THE CHAIN ASDATA2 (TDM ADC DATA IN) OF THE SECOND AD1937 ADCL1 ADCR1 IN THE CHAIN ...
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... MCLK LRCLK BCLK AUX ADC 2 DATA MCLK Figure 27. Example of TDM/AUX Mode Connection to SHARC® (AD1937 as TDM Master/AUX Master Shown) TDM Modes TDM ADC data out TDM ADC data in TDM DAC data in TDM DAC data out TDM DAC2 data in (dual-line mode) TDM DAC2 data out (dual-line mode) ...
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... DBCLK TDM DSDATAn (Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission; To relax the requirement for the setup time of the AD1937 in cases of high speed TDM data transmission, the AD1937 can latch in the data using the falling edge of DBCLK. This effec- tively dedicates the entire BCLK period to the setup time ...
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... CONTROL REGISTERS DEFINITIONS The global address for the AD1937 is 0x08 OR’ with ADDR1 and ADDR0 and one R/ W bit; see bits (Bits[18:17]) setting must correspond to the low/high state of Pin 30 and Pin 35. All registers are reset to 0, except for the DAC volume registers that are set to full volume ...
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... AD1937 Table 23. PLL and Clock Control 1 Register (Address 1, 0x01) Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS Table 24. DAC Control 0 Register (Address 2, 0x02) Bit Value Function ...
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... DBCLK master/slave DBCLK source DBCLK polarity Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Description DAC1L mute DAC1R mute DAC2L mute DAC2R mute DAC3L mute DAC3R mute DAC4L mute DAC4R mute Rev Page AD1937 ...
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... AD1937 Table 28. DACxx Volume Controls Registers (Address 6 to Address 13, 0x06 to 0x0D) Bit Value Function 7 attenuation 1 to 254 −0.375 dB per step 255 Full attenuation ADC CONTROL REGISTERS Table 29. ADC Control 0 Register (Address 14, 0x0E) Bit Value Function 0 0 Normal 1 Power down ...
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... Left high 3 0 Slave 1 Master 5 cycles 01 128 cycles 10 256 cycles 11 512 cycles 6 0 Slave 1 Master 7 0 ABCLK pin 1 Internally generated Description ALRCLK format ABCLK polarity ALRCLK polarity ALRCLK master/slave ABCLKs per frame ABCLK master/slave ABCLK source Rev Page AD1937 ...
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... AD1937 APPLICATIONS CIRCUITS Typical application circuits are shown in Figure 31 through Figure 34. Figure 31 shows a typical ADC input filter circuit. Recommended loop filters for LRCLK and MCLK as the PLL reference are shown in Figure 32. Output filters for the DAC outputs are shown in Figure 33 and a regulator circuit is shown in Figure 34. ...
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... COPLANARITY VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 35. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Package Description 64-Lead LQFP 64-Lead LQFP, 13” Tape and Reel Evaluation Board Rev Page AD1937 49 48 10.20 10. 0.27 0.22 0.17 Package Option ST-64-2 ST-64-2 ...
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... AD1937 NOTES Rev Page ...
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... NOTES Rev Page AD1937 ...
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... AD1937 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...