XCR3256XL-7PQ208I XILINX [Xilinx, Inc], XCR3256XL-7PQ208I Datasheet - Page 4

• Manufacturer Part Number: XCR3256XL-7PQ208I
• Description: 256 Macrocell CPLD
• Manufacturer: XILINX [Xilinx, Inc]

XCR3256XL 256 Macrocell CPLD
Timing Model
The XPLA3 architecture follows a simple timing model that
allows deterministic timing in design and redesign. The
basic timing model is shown in
the XPLA3 CPLD is the ability to have up to 48 product term
inputs into a single macrocell and maintain consistent tim-
ing. This is achieved through the use of a fully populated
PLA (Programmable AND Programmable OR Array) which
also has the ability to share product terms and only use the
required amount of product terms per macrocell. There is a
fast path (T
a single product term. The T
4
LOGI1
) into the macrocell which is used if there is
T
T
T
GCK
FIN
IN
LOGI2
Figure
path is used for multiple
T
T
2. One key feature of
LOGI1,2
LOGI3
Figure 2: XPLA3 Timing Model
www.xilinx.com
1-800-255-7778
T
F
T
product term timing. For optimization of logic, the XPLA3
CPLD architecture includes a Fold-back NAND path
(T
as an Input Register (T
control terms (T
the macrocell registers in different logic blocks. There is
also slew rate control and output enable control on a per
macrocell basis.
UDA
LOGI3
). There is a fast input path to each macrocell if used
UDA
DLT
CE
S/R
) that can be used for synchronization of
FIN
). XPLA3 also includes universal
Preliminary Product Specification
Q
DS013 (v1.2) May 3, 2000
T
T
T
OUT
EN
SLEW
DS017_02_042800
R