ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet - Page 12

• Manufacturer Part Number: ADSP-21267SKBCZ-X
• Description: Preliminary Technical Data
• Manufacturer: AD [Analog Devices]

ADSP-21267
Table 2. Pin Descriptions (Continued)
1
2
3
4
Pin
CLKIN
XTAL
CLKCFG1-0
RSTOUT/CLKOUT
RESET
TCK
TMS
TDI
TDO
TRST
EMU
V
V
A
A
GND
RD, WR, and ALE are continuously driven by the DSP and won’t be three-stated.
Output only is a three-state driver with its output path always enabled.
Input only is three-state driver with both output path.
Three-state is three-state driver.
DDINT
DDEXT
VDD
VSS
Type
I
O
I
O
I/A
I
I/S
I/S
O
I/A
O (O/D)
P
P
P
G
G
State During &
After Reset
Input only
Output only
Input only
Output only
Input only
Input only
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
Three-state with
pull-up enabled
Three-state with
pull-up enabled
PRELIMINARY TECHNICAL DATA
3
4
2
Rev. PrA | Page 12 of 44 | January 2004
Function
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21267 clock input.
It configures the ADSP-21267 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the ADSP-21267 to use the external clock source
such as an external clock oscillator. The core is clocked either by the PLL output or
this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See
on page 13
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
Reset Out/Local Clock Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTL register. The default is reset out.
Processor Reset. Resets the ADSP-21267 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21267.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a
22.5 k internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21267. TRST has
a 22.5 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21267 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a
22.5 k internal pullup resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor (13
pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the
LQFP package).
Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL
(clock generator). This pin has the same specifications as V
filtering circuitry is required.
Analog Power Supply Return.
Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
for a description of the clock configuration modes.
For more information, see Power Supplies on page 7.
DDINT
, except that added
Table 5