ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet - Page 27
ADSP-21267SKBCZ-X
Manufacturer Part Number
ADSP-21267SKBCZ-X
Description
Preliminary Technical Data
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-21267SKBCZ-X.pdf
(44 pages)
- Current page: 27 of 44
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Table 21. 16-bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
D = (Data Cycle Duration) x t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEW
ALERW
ADAS
ADAH
WW
ALEHZ
DWS
DWH
CCLK
(if a hold cycle is specified, else H = 0)
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data [15:0] Setup Before ALE Deasserted
Address/Data [15:0] Hold After ALE Deasserted
WR Pulse Width
ALE Deasserted
Address/Data [15:0] Setup Before WR High
Address/Data [15:0] Hold After WR High
CCLK
AD[15:0]
PRELIMINARY TECHNICAL DATA
ALE
WR
RD
1
to Address/Data[15:0] In High Z
Figure 20. Write Cycle For 16-bit Memory Timing
Rev. PrA | Page 27 of 44 | January 2004
VALID ADDRESS
t
ADAS
t
ALEW
t
ADAH
t
ALEHZ
1
1
t
ALERW
Min
2 x t
1 x t
2.5 x t
0.5 x t
D – 2
0.5 x t
D
0.5 x t
t
t
DWS
VALID DATA
CCLK
CCLK
WW
CCLK
CCLK
CCLK
CCLK
– 2
– 1
– 2.0
– 0.8
– 0.8
– 1.5 + H
t
DWH
Max
0.5t
CCLK
ADSP-21267
+ 3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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