ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 16

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks, including
USB clocks. Note that the USBCLK is provided for debug pur-
poses only and is not supported or guaranteed for clocking
customer applications. By default, the SYS_CLKOUT pin drives
a buffered version of the SYS_CLKIN input. Clock generation
faults (for example PLL unlock) may trigger a reset by hardware.
The clocks shown in
SYS_CLKOUT.
Table 3. Clock Dividers
Power Management
As shown in
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. There are no
sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate
cations
feature/peripheral is not used.
Table 4. Power Domains
The dynamic power management feature of the processor
allows the processor’s core clock frequency (f
ically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Clock Source
CCLK (core clock)
SYSCLK (System clock)
SCLK0 (system clock for PVP, all
peripherals not covered by
SCLK1)
SCLK1 (system clock for SPORTS,
SPI, ACM)
DCLK (LPDDR/DDR2 clock)
OCLK (output clock)
USBCLK
CLKBUF
USBCLKBUF
Power Domain
All internal logic
DDR2/LPDDR
USB
Thermal diode
All other I/O (includes SYS, JTAG, and Ports pins) V
table for processor operating conditions; even if the
Table
4, the processor supports five different power
Table 3
can be outputs from
Divider
By 4
By 2
None
None
By 2
Programmable
None
None, direct from SYS_CLKIN
None, direct from USB_CLKIN
CCLK
VDD Range
V
V
V
V
) to be dynam-
DD_INT
DD_DMC
DD_USB
DD_TD
DD_EXT
Rev. PrD | Page 16 of 44 | March 2012
Specifi-
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor cores and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clocks and system clocks
run at the input clock (SYS_CLKIN) frequency. DMA access is
available to appropriately configured L1 memories.
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF60x Blackfin Pro-
cessor Hardware Reference.
See
Table 5. Power Settings
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core and to all synchronous
peripherals. Asynchronous peripherals may still be running but
cannot access internal resources or external memory.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor cores and to all of the
peripherals. This setting signals the external voltage regulator
supplying the V
SYS_EXTWAKE signal, which provides the lowest static power
dissipation. Any critical information stored internally (for
example, memory contents, register contents, and other infor-
mation) must be written to a non-volatile storage device prior to
removing power if the processor state is to be preserved.
Since the V
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
Reset Control Unit
Reset is the initial state of the whole processor or one of the
cores and is the result of a hardware or software triggered event.
In this state, all control registers are set to their default values
Mode/State PLL
Full On
Active
Deep Sleep
Hibernate
Table 5
DD_EXT
for a summary of the power settings for each mode.
Enabled No
Enabled/
Disabled
Disabled —
Disabled —
DD_INT
Preliminary Technical Data
pins can still be supplied in this mode, all of
pins to shut off using the
PLL
Bypassed f
Yes
Enabled Enabled
Enabled Enabled
Disabled Disabled
Disabled Disabled
CCLK
f
f
f
f
SYSCLK
DCLK
SCLK0
SCLK1
,
,
,
Core
Power
On
On
On
Off