ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 3

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF609 processor is a member of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The processor offers performance up to 500 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation and power/motor con-
trol applications.
Table 1. Processor Comparison
Processor Feature
Up/Down/Rotary Counters
Timer/Counters with PWM
3-Phase PWM Units (4-pair)
SPORTs
SPIs
USB OTG
Parallel Peripheral Interface
Removable Storage Interface
CAN
TWI
UART
ADC Control Module (ACM)
Link Ports
Ethernet MAC (IEEE 1588)
Pixel Compositor (PIXC)
Pipelined Vision Processor
(PVP)
GPIOs
1
Table
1), Blackfin processors are the
No
No
112
1
8
2
3
2
1
3
1
1
2
2
1
4
2
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
VGA
Rev. PrD | Page 3 of 44 | March 2012
1
HD
1
Table 1. Processor Comparison (Continued)
1
2
BLACKFIN PROCESSOR CORE
As shown in
cessor cores. Each core, shown in
multipliers, two 40-bit accumulators, two 40-bit ALUs, four
video ALUs, and a 40-bit shifter. The computation units process
8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
Processor Feature
Maximum Speed Grade (MHz)
Maximum SYSCLK (MHz)
Package Options
VGA is 640 x 480 pixels per frame, 30 frames per second. HD is 1280 x 960 pixels
Maximum speed grade is not available with every possible SYSCLK selection.
per frame, 30 frames per second.
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L2 Data SRAM
L2 Boot ROM
Figure
1, the processor integrates two Blackfin pro-
32
multiply, divide primitives, saturation
2
128K
400
Figure
349-Ball CSP_BGA
2, contains two 16-bit
64K
16K
32K
32K
32K
250
4K
256K
500