ADSP21020 AD [Analog Devices], ADSP21020 Datasheet - Page 13

• Manufacturer Part Number: ADSP21020
• Description: 32/40-Bit IEEE Floating-Point DSP Microprocessor
• Manufacturer: AD [Analog Devices]

REV. C
TIMING PARAMETERS
General Notes
See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters
from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the
values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to
derive other specifications.
Clock Signal
Parameter
Timing Requirement:
t
t
t
Reset
Parameter
Timing Requirement:
t
t
NOTES
DT = t
1
2
WRST
SRST
Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low,
Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at
CK
CKH
CKL
assuming stable V
location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for reset sequence information.
2
1
CK
RESET Width Low
RESET Setup before CLKIN High 29
–50 ns
CLKIN Period
CLKIN Width High
CLKIN Width Low
DD
and CLKIN (not including clock oscillator start-up time).
RESET
CLKIN
K/B/T Grade
Min
50
10
10
CLKIN
K/B/T Grade K/B/T Grade B/T Grade
Min
200
20 MHz
20 MHz
Max Min
50
Max
150
160
24
Figure 4. Reset
Figure 3. Clock
25 MHz
t
t
CKH
WRST
Min
40
10
10
K/B/T Grade
–13–
Max
40
25 MHz
t
CK
Max
150
Min Max
132
21
30 MHz
t
CKL
33
Min
33
10
10
B/T Grade
Min Max
120
19
33.3 MHz
K Grade
30 MHz
t
SRST
30
Max
150
Frequency Dependency*
29 + DT/2
Min
4t
CK
Min
30
10
10
33.3 MHz
K Grade
ADSP-21020
Max
30
Max
150
Unit
ns
ns
ns
Unit
ns
ns