ADSP21020 AD [Analog Devices], ADSP21020 Datasheet - Page 26

• Manufacturer Part Number: ADSP21020
• Description: 32/40-Bit IEEE Floating-Point DSP Microprocessor
• Manufacturer: AD [Analog Devices]

ADSP-21020
ENVIRONMENTAL CONDITIONS
The ADSP-21020 is available in a Ceramic Pin Grid Array
(CPGA). The package uses a cavity-down configuration which
gives it favorable thermal characteristics. The top surface of the
package contains a raised copper slug from which much of the
die heat is dissipated. The slug provides a surface for mounting
a heat sink (if required).
The commercial grade (K grade) ADSP-21020 is specified for
operation at T
temperature) can be calculated from the following equation:
where PD is power dissipation and
thermal resistance. The value of PD depends on your
application; the method for calculating PD is shown under
“Power Dissipation” below.
presence or absence of a heat sink. Table IX shows a range of
Airflow (Linear ft./min.) 0
CPGA with No Heat Sink 12.8 C/W 9.2 C/W 6.6 C/W 5.5 C/W
NOTES
Maximum recommended T
As per method 1012 MIL-STD-883. Ambient temperature: 25 C. Power:
3.5 W.
Power Dissipation
Total power dissipation has two components: one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation is dependent on the
instruction execution sequence and the data values involved.
Internal power dissipation is calculated in the following way:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
1) the number of output pins that switch during each cycle (O),
2) the maximum frequency at which they can switch (f),
3) their load capacitance (C), and
4) their voltage swing (V
It is calculated by:
The load capacitance should include the processor’s package
capacitance (C
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2t
can switch every cycle at a frequency of 1/t
at 1/(2t
cycle. If only one bank is accessed, no select line will switch.
JC
CA
is approximately 1 C/W.
values.
Table IX. Maximum
CK
), but 2 DM and 2 PM selects can switch on each
AMB
IN
). The switching frequency includes driving the
T
of 0 C to +70 C. Maximum T
P
CASE
EXT
J
P
is 130 C.
INT
DD
= O
T
).
= I
CA
AMB
CA
DDIN
for Various Airflow Values
C
varies with airflow and with the
PD
CA
V
100
V
DD
DD
is the case-to-ambient
CK
2
CK
CA
). The write strobes
f
. Select pins switch
200
CASE
(case
300
–26–
Example:
Estimate P
•
•
•
•
•
The P
drive:
Pin
Type
PMA
PMS
PMWR
PMD
DMA
DMS
DMWR
DMD
A typical power consumption can now be calculated for this
situation by adding a typical internal power dissipation:
P
Note that the conditions causing a worst case P
from those causing a worst case P
occur while 100% of the output pins are switching from all ones
to all zeros. Also note that it is not common for a program to
have 100% or even 50% of the outputs switching simultaneously.
Power and Ground Guidelines
To achieve its fast cycle time, including instruction fetch, data
access, and execution, the ADSP-21020 is designed with high
speed drivers on all output pins. Large peak currents may pass
through a circuit board’s ground and power lines, especially
when many output drivers are simultaneously charging or
discharging their load capacitances. These transient currents can
cause disturbances on the power and ground lines. To minimize
these effects, the ADSP-21020 provides separate supply pins for
its internal logic (IGND and IVDD) and for its external drivers
(EGND and EVDD).
To reduce system noise at low temperatures when transistors
switch fastest, the ADSP-21020 employs compensated output
drivers. These drivers equalize slew rate over temperature
extremes and process variations. A 1.8 k resistor placed
between the RCOMP pin and EVDD (+5 V) provides a
reference for the compensated drivers. Use of a capacitor
(approximately 100 pF), placed in parallel with the 1.8 k
resistor, is recommended.
TOTAL
(32 bits).
switch at once.
pins switching.
V
A system with one RAM bank each of PM (48 bits) and DM
32K
Single-precision mode is enabled so that only 32 data pins can
PM and DM writes occur every other cycle, with 50% of the
The instruction cycle rate is 20 MHz (t
DD
EXT
= 5.0 V.
= P
= 1.36 W
8 RAM chips are used, each with a load of 10 pF.
equation is calculated for each class of pins that can
#
Pins Switch
15
2
1
32
15
2
1
32
EXT
EXT
with the following assumptions:
+ (5 V
%
50
0
—
50
50
0
—
50
18 pF 5 MHz
18 pF 5 MHz
I
68 pF 5 MHz
68 pF 5 MHz
68 pF 10 MHz 25 V
48 pF 5 MHz
48 pF 5 MHz
48 pF 10 MHz 25 V
DDIN
C
(typ)) = 0.210 + 1.15
INT
. Maximum P
f
CK
= 50 ns) and
25 V
25 V
25 V
25 V
25 V
25 V
EXT
V
DD
INT
P
are different
2
EXT
cannot
P
0.064 W
0.000 W
0.017 W
0.036 W
0.045 W
0.000 W
0.012 W
0.036 W
=0.210 W
EXT
REV. C