SAF7115ET NXP [NXP Semiconductors], SAF7115ET Datasheet - Page 17

• Manufacturer Part Number: SAF7115ET
• Description: Multistandard video decoder with super-adaptive comb filter,
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 7.
V
Figure 3
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Valid for output: XRDY
[11] Valid for outputs: IPD [7:0], HPD [7:0], IGPH, IGPV, IDQ, IGP1, IGP0
[12] Valid for input: ITRDY
SAF7115_1
Product data sheet
Symbol
t
t
Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b)
C
t
t
Data and control signal input timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b)
t
t
Data and control signal output timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 11b)
C
t
t
Data and control signal input timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 01b)
t
t
AMCLK clock output
C
t
t
r
f
h(Q)
PD
su(D)
h(D)
h(Q)
PD
su(D)
h(D)
r
f
DDD
o(L)
o(L)
o(L)
This setting connects pin AOUT to ground.
Controlled through chip enable input (CE) from normal operation mode at typical supply voltage of V
I
The ADC gain difference is
V
The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); C
The effects of rise and fall times are included in the calculation of t
illustrated in
Valid for outputs: XPD [7:0], XRH, XRV, XDQ, RTS0, RTS1, RTCO
Valid for inputs: XPD [7:0], HPD [7:0], XRH, XRV, XDQ
2
= 3.0 V to 3.6 V; V
CC(I2C-bus)
C-bus controlled through subaddress 88h set to xx00 1011b.
and
Characteristics
Figure
Parameter
rise time
fall time
output load capacitance at all outputs
data output hold time
propagation delay
data input set-up time
data input hold time
output load capacitance at all outputs
data output hold time
propagation delay
data input set-up time
data input hold time
output load capacitance
rise time
fall time
is the external supply voltage of the I
Figure 3
4; unless otherwise specified.
and
DDA
Figure
= 3.1 V to 3.5 V; T
…continued
G
ADC
4.
=
Conditions
0.6 V to 2.6 V
2.6 V to 0.6 V
from positive edge of LLC
output
0.6 V to 2.6 V
2.6 V to 0.6 V
maximum deviation
----------------------------------------------- - 1
minimum deviation
amb
2
C-bus (3.3 V or 5 V).
Rev. 01 — 15 October 2008
= 25 C; timings and levels refer to drawings and conditions illustrated in
–
h(Q)
100
and t
[11]
[11]
[12]
[12]
[11]
[11]
[12]
[12]
.
L
PD
= 50 pF.
Min
-
-
15
3
-
18
-
15
3
-
12
-
15
-
-
. Timings and levels refer to drawings and conditions
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Multistandard video decoder
DDD
= V
Max
5
5
50
-
23
-
50
-
23
-
2
50
5
5
DDA
2
SAF7115
© NXP B.V. 2008. All rights reserved.
= 3.3 V.
17 of 35
Unit
ns
ns
pF
ns
ns
ns
ns
pF
ns
ns
ns
ns
pF
ns
ns