SAA7127 PHILIPS [NXP Semiconductors], SAA7127 Datasheet - Page 31

• Manufacturer Part Number: SAA7127
• Description: Digital video encoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Explanation of RTCI data bits
1. The HPLL increment is not evaluated by SAA7126H; SAA7127H.
2. The SAA7126H; SAA7127H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.).
3. The PAL bit indicates the line with inverted (R
4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line
5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7126H; SAA7127H takes this bit instead of the FISE bit
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7126H; SAA7127H ignores it’s internally generated
7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0),
1999 May 31
handbook, full pagewidth
Digital video encoder
RTCI
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
whenever the reset bit of RTCI input is set to logic 1.
in subaddress 61H.
odd/even flag and takes the odd/even bit from RTCI input.
the subcarrier frequency is generated by the SAA7126H; SAA7127H. In the other case (colour detection bit = 1) the
subcarrier frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL
increment, independent of the colour detection bit of RTCI input.
H/L transition
count start
128
time slot:
LOW
not used in SAA7126H/27H
Y) line normal, 1 = (R
0 1
13
increment
HPLL
(1)
14
0
Y) line inverted; NTSC: 0 = no change.
reserved
4 bits
Fig.13 RTCI timing.
19
22
Y) component of colour difference signal.
31
FSCPLL increment
sample
valid
sample
invalid
(2)
SAA7126H; SAA7127H
8/LLC
reserved
3 bits
Product specification
64
0
67
68
MHB503
(3)
69 72 74
(4)
(5)
(6)
(8)
(7)