SAA7199BWP PHILIPS [NXP Semiconductors], SAA7199BWP Datasheet - Page 17

• Manufacturer Part Number: SAA7199BWP
• Description: Digital Video Encoder DENC GENLOCK-capable
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Modes of the SAA7199B
Table 18 The four different modes of the SAA7199B
R
1. Internal subcarrier frequency with n = integer
2. External subcarrier frequency
3. External HPLL increment
The absolute phase relationship between sync and subcarrier (colour burst output) can be influenced in all three events
by CHPS7 to CHPS0 register byte (index 0C).
1996 Sep 27
Stand alone
Slave
GENLOCK
Test
ELATIONSHIP BETWEEN HORIZONTAL FREQUENCY AND COLOUR SUBCARRIER FREQUENCY IN NON
Digital Video Encoder (DENC)
GENLOCK-capable
PAL: f
NTSC: f
Necessary conditions: non-GENLOCK mode; RTCE = 0, FSCO = 00H; phase coupling of the two frequencies is
given by a definite phase reset every 8th field at PAL (4th field at NTSC).
FSCO
f
Necessary conditions: Slave mode; RTCE = 1, RTSC = 1. The 8th respectively 4th field reset is enabled at
FSCO = 00H (disabled at FSCO
real time increment.
f
absolute crystal frequency value used by the digital colour decoder.
Necessary conditions: Slave mode; RTCE = 1, RTSC = 0. The 8th respectively 4th field reset is enabled at
FSCO = 00H (disabled at FSCO
SC
SC
MODE
is given by RTCI real time input from a digital colour decoder
is calculated by RTCI real time input signal from a digital colour decoder. The frequency of f
SC
SC
00H adjusts the subcarrier frequency, phase reset is disabled and phase between f
= f
= f
H
(n/4 + 1/625) respectively f
H
The SAA7199B receives a line-locked clock CLKIN and generates CSYN or HSN/VSN output
signals, which trigger the RGB or the YUV source signal to provide data and composite blanking CB.
The SAA7199B receives the line-locked clock CLKIN, CSYN or HSN/VSN, CB and data from an
RGB or YUV source. The sync inputs are edge-sensitive; their minimum active length is 1 PIXCLK.
A real time control signal RTCI is received from a digital colour decoder as an option.
Horizontal and vertical sync plus colour are locked on a received CVBS reference signal. The CVBS
reference signal also generates a line-locked clock by the SAA7197 clock generator. Auxiliary
signals HCL and HSY plus CSYN or HSN/VSN are generated to trigger the RGB or the YUV source
providing data and composite blanking CB.
Similar to stand alone mode, but the contents of the test registers TRER, TREG and TREB consists
of data to be encoded. VSN/CSYN and HSN outputs are in 3-state condition.
(n/2)
00H). The subcarrier frequency is not influenced by FSCO bits, but is given by
00H). The subcarrier frequency is influenced by FSCO bits.
H
(n/4 + 1/525)
17
DESCRIPTION
-GENLOCK
SC
and f
Product specification
SC
SAA7199B
depends on the
H
is not constant.
MODE