SAA7806H NXP [NXP Semiconductors], SAA7806H Datasheet - Page 42

• Manufacturer Part Number: SAA7806H
• Description: One chip automotive CD audio device
• Manufacturer: NXP [NXP Semiconductors]

Philips Semiconductors
9397 750 13697
Objective data sheet
6.6.7.10 EBU interface
The I
can be gated off by the channel decoder. In slave mode, the bclk is continuously running.
To prevent the internal FIFO from overflow, the filling of the buffer must be regulated (see
Section “Data latency and FIFO operation” on page
Bclk and WCLK can either be input (generated outside the channel decoder) or output
(generated internally in the clock control block). Selection can be done via bits WCLKSEL
and BCLKSEL in register IISConfig.
The I
register BitClockConfig. The I
6
In case of gated bit clock, when BitClockConfig(BCLKGEN) is ‘1’, the speed must be
configured such that the maximum rate available on the bus is 20 % higher than the
average data throughput rate. Or in other words: the bus should have at least 20 % idle
time in between 2 bursts of data.
Default after reset, the I
activated via register IISConfig. This register also contains the possibility to kill the I
interface, such that all dataline outputs go LOW.
The channel decoder contains a digital one wire EBU or SPDIF output interface. It formats
data according to the IEC60958 specification. The EBU rate can be selected to be 1 ,
2 , 4
For proper operation of the EBU interface, the I
generated, bitclock gating must be disabled and the following relationship between
EBUClk, bclk, WCLK and I
EBUClk = WCLK
Some fields in the user channel of the EBU-stream can be filled in by software, configured
via register EBUConfig.
Bit IISConfig(KILLEBU) contains the possibility to ‘kill’ the EBU interface, so that the line
outputs go LOW.
•
•
•
•
•
CD (not available for I
Bclk: all other I
WCLK: indicates the start of a new 16/18-bit word on the dataline, and differentiates
between left and right sample
DATA: 16/18-bit data words are outputted via this line, 1-bit / bclk-period
Error Flag (EF): contains the byte reliability flag; bytes that are indicated as erasures
(possible errors) after C1 and C2 correction, are flagged.
SYNC: indicates that the serial subcode line contains the MSB of a subcode word; it
will be asserted every six WCLK periods for half a WCLK period. If a subcode sync is
transferred on the subcode line, this signal will be asserted for a full WCLK period.
2
2
S-bus interface can either work in master or slave mode. In master mode, the bclk
S-bus output rate is determined by the speed of the bclk, which is configured via
or 6
CD, by programming register EBUClockConfig.
2
64
S-bus signals are clocked on bclk
Rev. 01 — 20 June 2005
2
S-bus pins on the IC will be put into 3-state. They can be
2
S-bus 24).
2
S-bus format must be true:
2
S-bus interface can be configured to run at 1 , 2 , 4
2
S-bus bit clock must be internally
One chip automotive CD audio device
35).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SAA7806
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S-bus
or