EPF8282A ALTERA [Altera Corporation], EPF8282A Datasheet
EPF8282A
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EPF8282A Summary of contents
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... January 2003, ver. 11.1 1 Features... Table 1. FLEX 8000 Device Features Feature EPF8282A EPF8282AV Usable gates Flipflops Logic array blocks (LABs) Logic elements (LEs) Maximum user I/O pins Altera Corporation DS-F8000-11.1 ® Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see – 2,500 to 16,000 usable gates – ...
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... Features Table 2. FLEX 8000 Package Options & I/O Pin Count Device 84- 100- Pin Pin PLCC TQFP EPF8282A 68 78 EPF8282AV 78 EPF8452A 68 68 EPF8636A 68 EPF8820A EPF81188A EPF81500A Note: (1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages ...
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Table 3. FLEX 8000 Performance Application 16-bit loadable counter 16-bit up/down counter 24-bit accumulator 16-bit address decode 16-to-1 multiplexer Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices provide a large number of storage elements for ...
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FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a ...
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Figure 1. FLEX 8000 Device Block Diagram I/O Element (IOE) IOE IOE Logic Array Block (LAB) IOE IOE Logic Element (LE) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Logic Array Block A logic array block (LAB) consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure ...
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Figure 3. FLEX 8000 LE DATA1 DATA2 DATA3 DATA4 LABCTRL1 LABCTRL2 LABCTRL3 LABCTRL4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these ...
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FLEX 8000 Programmable Logic Device Family Data Sheet The FLEX 8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports high- speed counters and adders; the ...
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Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX 8000 Carry Chain Operation Carry- Carry a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain Cascade Chain With ...
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FLEX 8000 Programmable Logic Device Family Data Sheet The MAX+PLUS II Compiler can create cascade chains automatically during design processing; designers can also insert cascade chain logic manually during design entry. Cascade chains longer than eight LEs are automatically implemented ...
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Figure 6. FLEX 8000 LE Operating Modes Normal Mode Carry-In data1 data2 data3 data4 Arithmetic Mode Carry-In data1 data2 Up/Down Counter Mode Carry-In data1 (ena) (nclr) data2 (data) data3 data4 (nload) Clearable Counter Mode Carry-In (ena) data1 (nclr) data2 data3 ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB ...
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Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus physical tri-state bus, the tri-state buffers’ output enable signals select the ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes Asynchronous Clear VCC PRN Q D CLRN LABCTRL1 or LABCTRL2 Asynchronous Load with Clear NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT LABCTRL2 ...
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Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An ...
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FLEX 8000 Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 8000 architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal (row) and vertical (column) routing channels that ...
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... input from an I/O pin, must transfer to the row interconnect before it can enter an LAB. summarizes the FastTrack Interconnect resources available in each FLEX 8000 device. Table 4. FLEX 8000 FastTrack Interconnect Resources Device Rows Channels per Row EPF8282A 2 EPF8282AV EPF8452A 2 EPF8636A 3 EPF8820A 4 EPF81188A 6 EPF81500A ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Figure 9. FLEX 8000 Device Interconnect Resources Each LAB is named according to its physical row ( etc.) and column ( etc.) position within the device. IOE Column ...
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... The size of the multiplexer varies with the number of columns in a device. EPF81500A devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to each side of the row channels ...
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... Each IOE is driven by an n-to-1 multiplexer. Note: ( for EPF8282A and EPF8282AV devices for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices for EPF81500A devices. Column-to-IOE Connections Two IOEs are located at the top and bottom of the column channels (see Figure separate column channels. The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer ...
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Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX 8000 Column-to-IOE Connections Each IOE is driven by an IOE 8-to-1 multiplexer. 8 Column Interconnect In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated ...
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... Figure peripheral bus correlates to the number of columns in the FLEX 8000 device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and EPF81500A devices use 27 channels. The first LE in each LAB is the source of the row channel signal ...
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... Table 5. Row Sources of FLEX 8000 Peripheral Control Signals Peripheral EPF8282A Control Signal EPF8282AV Row A CLK0 Row B CLK1/OE1 Row A CLR0 Row B CLR1/OE0 Row A OE2 Row B OE3 – OE4 – OE5 – OE6 – OE7 – OE8 – OE9 Output Configuration f Altera Corporation ...
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... JTAG instructions shown in Boundary-Scan Support Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. ...
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... The instruction register length for FLEX 8000 devices is three bits. shows the boundary-scan register length for FLEX 8000 devices. FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms Table 8 EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. ...
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... AC test measurements for FLEX 8000 devices are made under conditions equivalent to those shown in Figure 15. Designers can use multiple test patterns to configure devices during all stages of the production flow. EPF8282A Unit EPF8282AV EPF8636A EPF8820A EPF81500A Min Max 100 ns ...
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Figure 15. FLEX 8000 AC Test Conditions Operating Tables 9 recommended operating conditions, operating conditions, and Conditions capacitance for 5.0-V FLEX 8000 devices. Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings Symbol Parameter V Supply voltage ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal logic CCINT and input buffers V Supply voltage for output CCIO buffers, 5.0-V operation Supply voltage ...
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Table 12. FLEX 8000 5.0-V Device Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input is –0.5 V. During transitions, the inputs ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 15. FLEX 8000 3.3-V Device DC Operating Conditions Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL I ...
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... Figure 16. Output Drive Characteristics of 5.0-V FLEX 8000 Devices (Except EPF8282A) 200 150 Typical I O Output Current (mA) 100 Output Voltage (V) Figure 17 EPF8282A devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V Figure 18 devices. ...
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... FLEX 8000 Programmable Logic Device Family Data Sheet Timing Model 32 Figure 18. Output Drive Characteristics of EPF8282AV Devices 100 75 Typical I O Output 50 Current (mA) 25 The continuous, high-performance FastTrack Interconnect routing structure ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance ...
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Table 17. FLEX 8000 Internal Timing Parameters Symbol t IOE register data delay IOD t IOE register control signal delay IOC t Output enable delay IOE t IOE register clock-to-output delay IOCO t IOE combinatorial delay IOCOMB t IOE register ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 19. FLEX 8000 Interconnect Timing Parameters Symbol t Cascade delay between LEs in different LABs LABCASC t Carry delay between LEs in different LABs LABCARRY t LAB local interconnect delay LOCAL ...
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ROW Carry-In from Cascade-In from Previous LE Previous LE Cascade Gate Delay LUT Delay t LUT t t RLUT GATE t CLUT Carry Chain Delay t t LOCAL CGEN t CGENR t CICO Register Control CASC ...
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... FLEX 8000 Programmable Logic Device Family Data Sheet Table 21. FLEX 8000 Timing Model Interconnect Paths Source LE-Out LE-Out LE-Out LE-Out LE-Out IOE on row IOE on column Table 22. EPF8282A Internal I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
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... Table 23. EPF8282A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 4.2 2.5 5.0 7.2 5.0 A-4 Max Min Max 0.3 0.4 0.3 0.4 0.6 0.8 4.2 4.2 2.5 2.5 5.0 5.5 7.2 7.2 5.0 5.5 Unit ...
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... Table 24. EPF8282A LE Timing Parameters Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB PRE t CLR Table 25. EPF8282A External Timing Parameters Symbol Min t DRR t 1.0 ODH 38 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 15.8 1.0 A-4 Max Min Max 2 ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 26. EPF8282AV I/O Element Timing Parameters Symbol A-3 Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.8 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 27. EPF8282AV Interconnect Timing Parameters Symbol A-3 Min t LABCASC ...
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... FLEX 8000 Programmable Logic Device Family Data Sheet 40 Table 28. EPF8282AV Logic Element Timing Parameters Symbol A-3 Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB PRE t CLR Table 29. EPF8282AV External Timing Parameters Symbol A-3 Min t DRR t 1 ...
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Table 30. EPF8452A I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 32. EPF8452A LE Timing Parameters Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4.0 CL ...
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Table 34. EPF8636A I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 36. EPF8636A LE Timing Parameters Symbol t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR ...
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Table 38. EPF8820A I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 40. EPF8820A LE Timing Parameters Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4.0 CL ...
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Table 42. EPF81188A I/O Element Timing Parameters Symbol t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 44. EPF81188A LE Timing Parameters Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4.0 CL ...
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Table 46. EPF81500A I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 48. EPF81500A LE Timing Parameters Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4.0 CL ...
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Power The supply power (P) for FLEX 8000 devices can be calculated with the following equation: Consumption Typical I Table 15 on page 30. The P load characteristics and switching frequency, can be calculated using the guidelines ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Configuration & Operation f 52 Figure 20. FLEX 8000 I CCACTIVE 5.0-V FLEX 8000 Devices 1,000 800 600 I Supply CC Current (mA) 400 200 0 3.3-V FLEX 8000 Devices 100 90 ...
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Operating Modes The FLEX 8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation. The process of physically loading the SRAM programming data into the device is called configuration. During ...
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... ADD5 69 ADD4 70 ADD3 71 ADD2 76 ADD1 54 Tables 52 through 54 show the pin names and numbers for the dedicated pins in each FLEX 8000 device package. 84-Pin 100-Pin PLCC TQFP EPF8452A EPF8282A EPF8636A EPF8282AV 100 ...
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... TRST Dedicated 12, 31, 54, Inputs (10) 73 17, 38, 59, VCCINT 80 – VCCIO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 84-Pin 100-Pin 100-Pin PLCC TQFP EPF8452A EPF8282A EPF8452A EPF8636A EPF8282AV ...
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... EPF8282A 5, 26, 47 26, 47, GND No Connect – (N.C.) Total User I/O 64 Pins (9) 56 84-Pin 100-Pin 100-Pin PLCC TQFP EPF8452A EPF8282A EPF8452A EPF8636A EPF8282AV 2, 13, 30, 44, 19, 44, 69, 68 52, 63, 80 – – 13, 30, 37, 42, 43, 50, 52, 56, 63, 80, 87, 92, 93 144-Pin 160-Pin TQFP ...
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Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part Pin Name 160-Pin PQFP EPF8452A (2) 120 nSP (2) 117 MSEL0 (2) 84 MSEL1 (2) 37 nSTATUS (2) 40 nCONFIG (2) 1 DCLK 4 CONF_DONE (2) ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 53. FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part Pin Name 160-Pin PQFP EPF8452A 154 DATA4 157 DATA3 159 DATA2 11 DATA1 12 DATA0 (3) 128 SDOUT ...
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Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part Pin Name 225-Pin BGA EPF8820A (2) A15 nSP (2) B14 MSEL0 (2) R15 MSEL1 (2) P2 nSTATUS (2) R1 nCONFIG (2) B2 DCLK (2) ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part Pin Name 225-Pin BGA EPF8820A A5 DATA4 B5 DATA3 E6 DATA2 D5 DATA1 C4 DATA0 (3) ...
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Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part Pin Name 225-Pin BGA EPF8820A B1, D4, E14, GND F7, F8, F9, F12, G6, G7, G8, G9, G10, H1, H4, H5, H6, H7, H8, ...
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FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) Perform a complete thermal analysis before committing a design to this device package. See (Evaluating Power for Altera Devices) (2) This pin is a dedicated pin and is ...