EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 12

• Manufacturer Part Number: EP1C20F
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
Figure 2–5. Cyclone LE
2–6
Preliminary
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
addnsub
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock &
LAB Carry-In
Select
Carry-In1
Carry-In0
Look-Up
Table
(LUT)
Each LE's programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the LUT output
bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
Chain
Carry
Register chain
routing from
previous LE
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
Packed
Register Select
ADATA
D
ENA
PRN/ALD
CLRN
Register
Feedback
Q
Programmable
Register
Altera Corporation
LUT chain
routing to next LE
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Local Routing
Register chain
output
May 2008