XC2S100-5CS144C XILINX [Xilinx, Inc], XC2S100-5CS144C Datasheet
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XC2S100-5CS144C
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XC2S100-5CS144C Summary of contents
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... Device Cells (Logic and RAM) XC2S15 432 15,000 XC2S30 972 30,000 XC2S50 1,728 50,000 XC2S100 2,700 100,000 XC2S150 3,888 150,000 XC2S200 5,292 200,000 Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...
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Spartan-II 2.5V FPGA Family: Introduction and Ordering Information General Overview The Spartan-II family of FPGAs have a regular, flexible, pro- grammable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked ...
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... Table 3: Spartan-II User I/O Chart Maximum Device User I/O VQ100 XC2S15 86 XC2S30 132 XC2S50 176 XC2S100 196 XC2S150 260 XC2S200 284 Notes: 1. All user I/O counts do not include the four global clock/user input pins. DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification Spartan-II 2.5V FPGA Family: Introduction and Ordering Information global clock pins are usable as additional user I/Os when not used as a global clock pin ...
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... Ordering Information Example: Device Type Speed Grade Device Ordering Options Device Speed Grade XC2S15 -5 Standard Performance XC2S30 -6 Higher Performance XC2S50 XC2S100 XC2S150 XC2S200 Revision History Version No. Date 2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature range information. 2.1 10/31/00 Removed Power down feature ...