XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 4
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XC2S100-5CS144I
Manufacturer Part Number
XC2S100-5CS144I
Description
Spartan-II FPGA Family
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC2S100-5CS144I.pdf
(99 pages)
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Spartan-II Product Availability
Table 2
device/package combination. The four global clock pins are usable as additional user I/Os when not used as a global clock
pin. These pins are not included in user I/O counts.
Table 2: Spartan-II FPGA User I/O Chart
DS001-1 (v2.8) June 13, 2008
Product Specification
Notes:
1.
2.
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
All user I/O counts do not include the four global clock/user input pins.
Discontinued by PDN2004-01.
shows the maximum user I/Os available on the device and the number of user I/Os available for each
R
Maximum
User I/O
176
176
260
284
86
92
VQG100
VQ100
60
60
-
-
-
-
(1)
TQG144
TQ144
Available User I/O According to Package Type
86
92
92
92
-
-
www.xilinx.com
Spartan-II FPGA Family: Introduction and Ordering Information
CSG144
(Note 2)
CS144
92
-
-
-
-
PQG208
(Note 2)
PQ208
140
140
140
140
-
FGG256
FG256
176
176
176
176
-
-
Module 1 of 4
FGG456
(Note 2)
FG456
260
284
-
-
-
4
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