XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 56

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
2.
Propagation Delays
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
T
T
Set/Reset Delays
T
IOPICKD
IOICECK
IOPICK
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table
A zero hold time listing indicates no hold time or a negative hold time.
T
Symbol
T
T
T
T
T
T
IOSRCKI
T
IOCKIQ
IOSRIQ
IOPLID
GSRQ
IOPID
IOPLI
"IOB Input Delay Adjustments for Different Standards," page
IOPI
/ T
/ T
/ T
R
IOICKP
IOICKPD
IOCKICE
Pad to I output, no delay
Pad to I output, with delay
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
Clock CLK to output IQ
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
Description
(1)
(1)
(2)
www.xilinx.com
Spartan-II FPGA Family: DC and Switching Characteristics
XC2S100
XC2S150
XC2S200
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
XC2S15
XC2S30
XC2S50
Device
57.
All
All
All
All
All
All
All
All
All
"Delay Measurement Methodology," page
0.9 / 0.01
1.7 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.8 / 0
3.9 / 0
3.9 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Speed Grade
Max
0.8
1.5
1.7
3.8
3.8
3.8
3.8
4.0
4.0
0.7
1.1
1.5
9.9
-
-
-
-
-
-
-
-
0.9 / 0.01
1.9 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.4 / 0
4.6 / 0
4.6 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max
11.7
Module 3 of 4
1.0
1.8
2.0
4.5
4.5
4.5
4.5
4.7
4.7
0.8
1.2
1.7
-
-
-
-
-
-
-
-
Units
60.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
56