XC4VFX20 XILINX [Xilinx, Inc], XC4VFX20 Datasheet - Page 50

• Manufacturer Part Number: XC4VFX20
• Description: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Table 61: Sample Window
Table 62: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out
Production Stepping
The Virtex-4 FPGA stepping identification system denotes
the capability improvement of production released devices.
By definition, devices from one stepping are functional
supersets of previous devices. Bitstreams compiled for a
device with an earlier stepping are guaranteed to operate
correctly in subsequent device steppings.
New device steppings can be shipped in place of earlier
device steppings. Existing production designs are guaran-
teed on new device steppings. To take advantage of the
capabilities of a newer device stepping, customers are able
to order a new stepping version and compile a new bit-
stream.
Production devices are marked with a stepping version, with
the exception of some step 1 devices. Designs should be
compiled with a CONFIG STEPPING parameter set to a
specific stepping version. This parameter is set in the UCF
file:
The default stepping level used by the ISE software is
reported in the PAR report.
Table 63
DS302 (v3.2) April 10, 2008
Product Specification
Notes:
1.
2.
T
T
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Pin-to-Pin Clock-to-Out Using BUFIO
SAMP
SAMP_BUFIO
T
T
CONFIG STEPPING = “#”; (where # is the stepping
version)
This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
PSCS
ICKOFCS
Symbol
shows the JTAG ID code by step.
Symbol
/ T
PHCS
R
Sampling Error at Receiver Pins
Sampling Error at Receiver Pins using BUFIO
Setup/Hold of I/O clock across multiple clock regions
Clock-to-Out of I/O clock across multiple clock regions
Description
Description
(1)
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(2)
Table 63: JTAG ID Code by Step
Notes:
1.
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VLX100
XC4VLX160
XC4VLX200
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Shaded cells represent devices not produced at that stepping.
Device
Device
All
All
Step 0
0 or 2
2
2
0
0
–0.45
0.97
4.10
-12
450
350
-12
Speed Grade
Speed Grade
–0.45
1.08
4.54
Step 1
500
400
-11
-11
2 or 3
2 or 3
0 or 3
0 or 3
3
9
3
3
2
2
2
6
0
8
6
4
–0.44
1.17
5.02
550
450
-10
-10
Step 2
4 or 5
4 or 5
4 or 5
2 or 5
A
5
5
5
4
4
4
Units
Units
ps
ps
ns
ns
50