CY8C20111_12 CYPRESS [Cypress Semiconductor], CY8C20111_12 Datasheet
CY8C20111_12
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CY8C20111_12 Summary of contents
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CapSense ® Express™ – One Button and Two Button Capacitive Controllers Features Capacitive button input tied to a configurable output ■ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC ...
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Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Pinouts .............................................................................. 4 Pin Definitions .................................................................. 4 Typical Circuits ................................................................. 5 Operating Modes .............................................................. 8 Normal Mode ............................................................... 8 Setup Mode ................................................................. 8 I2C Interface ...................................................................... 8 I2C Device Addressing ................................................ 8 ...
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Pinouts Pin Definitions 8-pin SOIC CY8C20111 (1 Button) Pin No Name 1 V Ground I2C SCL I C Clock 2 3 I2C SDA I C Data 4 CS0 CapSense Input Connect 6 DIG0 Digital ...
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Pinouts Pin Definitions 8-pin SOIC CY8C20121 (2 Button) Pin No Name 1 V Ground I2C SCL I C Clock 2 3 I2C SDA I C Data 4 CS0 CapSense Input 5 CS1 CapSense Input 6 DIG0 Digital ...
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Typical Circuits Figure 4. Circuit-2: One Button and One LED with I Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. *H Figure 3. Circuit-1: One Button ...
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Typical Circuits (continued) Figure 5. Circuit-3: Two Buttons and Two LEDs with I Figure 6. Circuit-4: Compatibility with 1 Note 2. 1.8 V V _I2C V _CE and 2.4 V The ...
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Typical Circuits (continued) Figure 7. Circuit-5: Powering Down CapSense Express Device for Low Power Requirements Output enable Master Or Host Note 4. For low power requirements, if VDD turned off, the above concept can be used. The ...
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Operating Modes Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D ...
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Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr Register read format Start Slave Addr + W A Reg Addr Start Slave Addr + R A Data Legends Master A – ACK ...
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Register Map Register Name Address (in Hex) OUTPUT_PORT 04 CS_ENABLE 07 DIG_ENABLE 08 SET_STRONG_DM 11 OP_SEL_0 1C LOGICAL_OPR_INPUT0 1E [7] OP_SEL_1 21 [7] LOGICAL_OPR_INPUT1 23 CS_NOISE_TH 4E CS_BL_UPD_TH 4F CS_SETL_TIME 50 CS_OTH_SET 51 CS_HYSTERISIS 52 CS_DEBOUNCE 53 CS_NEG_NOISE_TH 54 CS_LOW_BL_RST ...
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Register Map (continued) Register Name Address (in Hex) CS_READ_STATUS 88 COMMAND_REG A0 CapSense Express Commands [8] Command Description Get firmware revision Store current configuration to NVM Restore factory ...
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OUTPUT_STATUS Output Status Register OUTPUT_STATUS: 00h 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name The Output Status register represents the actual logical levels on the output pins. Bit Name 1:0 STS [1:0] ...
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This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit Name 1:0 CS [1:0] DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only in ...
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LOGICAL_OPR_INPUT0 [0] ENB CS0 OP_SEL_0 [0] LOGICAL_OPR_INPUTx [0] ENB CS0 LOGICAL_OPR_INPUTx [1] ENB CS1 INPUT SELECTION LOGIC Document Number: 001-53516 Rev. *H Figure 10. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] INVERSION LOGIC OP_SEL_0 [1] Figure 11. CY8C20121 Digital Logic Diagram ...
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OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch OP_SEL_1: 21h (Not available for 1 Button) 1/2Button 7 6 Access: FD RW: 0 Bit Name Op_En This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to ...
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CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 6 Access: FD Bit Name This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to baseline. ...
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CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 6 Access: FD Bit Name CS_CLK[1:0] The registers set the CapSense module frequency of operation and enables or disables the sensor auto ...
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CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button 7 Access: FD Bit Name The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference count value ...
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CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 6 Access: FD RW: 0 Bit Name RstBl This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit Name 7 ...
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CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h CS_FINGER_TH_1: 67h (Not available in 1 Button) 1/2 Button 7 6 Access: FD Bit Name This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter should ...
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DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name This register contains the device and product ID. The device and product ID corresponds to “xx” in CY8C201xx. ...
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I2C_ADDR_DM 2 2 Device I C Address and I C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 6 Access: FD RW: 0 Bit Name I2CIP_EN 2 This register sets the drive mode pins and I ...
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CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h CS_READ_BLL: 83h 1/2 Button 7 6 Access: FD Bit Name Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit Name 7:0 BL [7:0] CS_READ_DIFFx Difference Count ...
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CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ indicates ...
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Command Name Code 04h Read POR Defaults 05h Read Device Configuration (RAM) 06h Reconfigure Device (POR) 07h Set Normal Operation Mode 08h Set Setup Operation Mode 09h Start CapSense Scanning 0Ah Stop CapSense Scanning 0Bh Returns CapSense Scanning Status Document ...
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Layout Guidelines and Best Practices Table 2. Layout Guidelines and Best Practices Sl. No. Category 1 Button Shape 2 Button Size 3 Button Button Spacing 4 Button Ground Clearance 5 Ground Flood – Top Layer 6 Ground Flood – Bottom ...
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X: Button to ground clearance Y: Button to button clearance Document Number: 001-53516 Rev. *H Figure 12. Button Shapes Figure 13. Button Layout Design Figure 14. Recommended Via-hole Placement CY8C20111, CY8C20121 Page ...
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Example PCB Layout Design with Two CapSense Buttons and Two LEDs Document Number: 001-53516 Rev. *H Figure 15. Top Layer Figure 16. Bottom Layer CY8C20111, CY8C20121 Page ...
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Operating Voltages For details on I2C 1x Ack time, refer Table on page 10 mentioned in these tables. CapSense Constraints Parameter Parasitic Capacitance ( the CapSense P Sensor Supply Voltage Variation ( Document Number: 001-53516 Rev. ...
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Absolute Maximum Ratings Parameter Description T Storage temperature STG T Bake Temperature BAKETEMP t Bake Time BAKETIME T Ambient temperature with power A applied V Supply voltage input voltage ...
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Electrical Specifications DC Electrical Specifications DC Chip Level Specifications Table 3. DC Chip Level Specifications Parameter Description V Supply voltage DD I Supply current DD DC GPIO Specifications Table 4 lists guaranteed maximum and minimum specifications for the voltage and ...
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DC Flash Write Specifications Table 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4. 5.25 V and –40 °C < T < 85 °C, 3. 3.6 V and –40 °C < ...
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CapSense Electrical Characteristics Max (V) Typ (V) Min (V) 3.6 3.3 3.1 2.90 2.7 2.45 5.25 5.0 4.75 AC Electrical Specifications AC Chip-Level Specifications Table 9. 5-V and 3.3-V AC Chip-Level Specifications Parameter Description F Internal low-speed oscillator 32K1 (ILO) ...
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Table 12. 2.7-V AC GPIO Specifications Parameter Description t Rise time, strong mode, Rise Cload = Fall time, strong mode, Fall Cload = Specifications 2 Table 13 Specifications ...
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Appendix 2 Examples of Frequently Used I C Commands SI. No. Requirement 1 Enter into setup mode 2 Enter into normal mode 3 Load factory defaults to RAM registers software reset 5 Save current configuration to flash ...
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Ordering Information Package Ordering Code Diagram CY8C20111-SX1I 51-85066 8-pin SOIC CY8C20111-SX1IT 51-85066 8-pin SOIC (Tape and Reel) CY8C20121-SX1I 51-85066 8-pin SOIC CY8C20121-SX1IT 51-85066 8-pin SOIC (Tape and Reel) Note For Die sales information, contact a local Cypress sales office or ...
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Package Diagram Figure 18. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066 Document Number: 001-53516 Rev. *H CY8C20111, CY8C20121 51-85066 *E Page ...
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Acronyms Table 16 lists the acronyms that are used in this document. Table 16. Acronyms Used in this Datasheet Acronym Description AC alternating current CMOS complementary metal oxide semiconductor CRC cyclic redundancy check CSA capsense successive approximation CSD capsense sigma ...
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Glossary active high 1. A logic signal having its asserted state as the logic 1 state logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. ...
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Glossary (continued) cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus ...
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Glossary (continued) low-voltage A circuit that senses V detect (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing ...
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Glossary (continued) settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or ...
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Document History Page Document Title: CY8C20111/CY8C20121, CapSense Document Number: 001-53516 Orig. of Rev. ECN No. Change ** 2709248 SLAN / PYRS *A 2821828 SSHH / FSU *B 2868929 SLAN *C 2892629 NJF *D 3043236 ARVM *E 3087790 NJF *F 3148656 ...
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