MM908E621ACDWB/R2 FREESCALE [Freescale Semiconductor, Inc], MM908E621ACDWB/R2 Datasheet - Page 58

• Manufacturer Part Number: MM908E621ACDWB/R2
• Description: Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
package independently heating with P
temperatures, T
temperature while only heat source 1 is heating with P
reference temperature while heat source 2 is heating with P
R
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Standards
Table 24. Thermal Performance Comparison
58
908E621
Additional Information
Thermal Addendum
Notes:
INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER
θ J21
Resistance
Thermal Addendum
Introduction
This thermal addendum ia provided as a supplement to the MM908E621
Package and Thermal Considerations
This MM908E621 is a dual die package. There are two heat sources in the
For m, n = 1, R
For m = 1, n = 2, R
1.
2.
3.
4.
5.
The stated values are solely for a thermal performance comparison of one
R
R
R
R
Thermal
θ
θ
θ
θJCmn
JAmn
JBmn
JAmn
and R
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
(5)
(1)(2)
(2)(3)
(1)(4)
WITH EMBEDDED MCU AND LIN FOR MIRROR
θ J22
T
T
J1
, respectively.
J1
J2
θ JA11
and T
m = 1,
1 = Power Chip, 2 = Logic Chip
n = 1
=
9.0
1.0
23
52
θ JA12
is the thermal resistance from Junction 1 to the reference
J2
R
R
θ JA21
, and a thermal resistance matrix with R
θ JA11
is the thermal resistance from Junction 1 to the
m = 1, n = 2
m = 2, n = 1
R
R
θ JA12
θ JA22
6.0
20
47
0
1
and P
.
ADDITIONAL INFORMATION
2
P
P
. This results in two junction
1
2
THERMAL ADDENDUM
[°C/W]
m = 2,
n = 2
2.0
24
10
52
1
.
2
. This applies to
θ JA mn
Figure 34. Thermal Land Pattern for Direct Thermal
.
10.3 mm x 5.1 mm Exposed Pad
17.9 mm x 7.5 mm Body
54 Terminal SOIC-EP
Attachment Per JEDEC JESD51-5
0.65 mm Pitch
Note For package dimensions, refer to the
908E621 device datasheet.
Analog Integrated Circuit Device Data
54-TERMINAL SOICW-EP
54-TERMINAL
98ARL105910
DWB SUFFIX
908E621
SOICW-EP
Freescale Semiconductor
0.2
* All measurements
are in millimeters
Soldermast
openings
Thermal vias
connected to top
buried plane
1.0
0.2
1.0