MM908E624ACEW/R2 FREESCALE [Freescale Semiconductor, Inc], MM908E624ACEW/R2 Datasheet - Page 28

• Manufacturer Part Number: MM908E624ACEW/R2
• Description: Integrated Triple High Side Switch with Embedded MCU and LIN Serial Communicationfor Relay Drivers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

908E624 SPI INTERFACE AND CONFIGURATION
link between the microcontroller and the analog die of the
908E624.
transfer is prepared.
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
moved to MISO/MOSI terminals. With the falling edge of the
SPI clock SPSCK the data is sampled by the Receiver.
28
908E624
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The serial peripheral interface creates the communication
The interface consists of four terminals (see
•
During the inactive phase of the
The falling edge of the
With the rising edge of the SPI clock, SPSCK the data is
SS
— Slave Select
SPSCK
MOSI
MISO
SS
Change MISO/MOSI Output
Read data latch
Rising edge of SPSCK
SS
indicates the start of a new data
SS
(HIGH), the new data
LOGIC COMMANDS AND REGISTERS
D7
D7
Falling edge of SPSCK
Sample MISO/MOSI Input
Figure
D6
D6
Figure 17. SPI Protocol
17):
D5
D5
Register write data
Register read data
D4
D4
The master sends 8 bits of control information and the slave
replies with 8 bits of status data.
edges are present in the active (low) phase of
the transfer and latches the write data (MOSI) into the
register The
state.
• MOSI — Master-Out Slave-In
• MISO — Master-In Slave-Out
• SPSCK — Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The data transfer is only valid if exactly 8 sample clock
The rising edge of the slave select
D3
D3
D2
D2
SS
D1
D1
high forces MISO to the high impedance
D0
D0
Analog Integrated Circuit Device Data
Write data latch
Freescale Semiconductor
SS
indicates the end of
SS
.