SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 15

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 38-08008 Rev. *D
Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control
bits.
Table 28. Control Register 1 [Address 05h]
Table 29. J-K Force-state Control Bits
Bit Position
Reserved
JK-Force State
7
6
5
4
3
2
1
0
7
0
0
1
1
Reserved
STBYD
SPSEL
J-K1
J-K0
DMA Dir
DMA Enable
USB Enable
Bit Name
STBYD
6
USB Engine Reset
SPSEL
Reserved bit - must be set to '0'.
XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’.
Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable) = ‘0’.
Speed Select. ‘0’ selects full speed. ‘1’ selects low speed (also see
J-K1 and J-K0 force state control bits are used to generate various USB bus conditions.
Forcing K-state is used for Peripheral device remote wake-up, Resume, and other modes.
These two bits are set to zero on power up, see
DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to
‘0’ for DMA WRITE cycles.
Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count
High is written.
Overall Enable for Transfers. ‘1’ enables and’ ‘0 disables. Set this bit to ‘1’ to enable USB
communication. Default at power up = ‘0’
Function
5
0
1
0
1
J-K1
4
Normal operating mode
Force SE0, D+ and D– are set low
Force K-State, D– set high, D+ set low
Force J-State, D+ set high, D– set low
J-K0
3
DMA Dir
Table 29
2
Function
for functions.
DMA Enable
1
Table 34 on page
SL811HS
Page 15 of 32
USB Enable
0
17).
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