KSZ8041NLAM MICREL [Micrel Semiconductor], KSZ8041NLAM Datasheet - Page 30

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KSZ8041NLAM

Manufacturer Part Number
KSZ8041NLAM
Description
10Base-T/100Base-TX Physical Layer Transceiver
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
Micrel, Inc.
Note:
1.
July 2008
Address
1f.11
1f.10
1f.9
1f.8
1f.7
1f.6
1f.5
1f.4:2
1f.1
1f.0
RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
Disable Data
Name
Force Link
Power Saving
Interrupt Level
Enable Jabber
Auto-
Negotiation
Complete
Enable Pause
(Flow Control)
PHY Isolate
Operation
Mode
Indication
Enable SQE
test
Scrambling
Description
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allow
transmitter to send pattern even if there is no
link.
1 = Enable power saving
0 = Disable power saving
If power saving mode is enabled and the cable
is disconnected, the RXC clock output (in MII
mode) is disabled. RXC clock is enabled after
the cable is connected and link is established.
1 = Interrupt pin active high
0 = Interrupt pin active low
1 = Enable jabber counter
0 = Disable jabber counter
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
1 = Flow control capable
0 = No flow control capability
1 = PHY in isolate mode
0 = PHY in normal operation
[000] = still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
1 = Enable SQE test
0 = Disable SQE test
1 = Disable scrambler
0 = Enable scrambler
30
Mode
RW
RW
RW
RW
RW
RO
RO
RO
RW
RW
(1)
Default
0
0
0
1
0
0
0
000
0
0
M9999-071808-1.2
KSZ8041NL

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