KSZ8041NLAM MICREL [Micrel Semiconductor], KSZ8041NLAM Datasheet - Page 9

• Manufacturer Part Number: KSZ8041NLAM
• Description: 10Base-T/100Base-TX Physical Layer Transceiver
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
Pin Description
July 2008
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin Number
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
TX+
XO
XI /
REFCLK
REXT
MDIO
MDC
RXD3 /
PHYAD0
RXD2 /
PHYAD1
RXD1 /
RXD[1] /
PHYAD2
RXD0 /
RXD[0] /
DUPLEX
VDDIO_3.3
RXDV /
CRSDV /
CONFIG2
RXC
Pin Name
Gnd
P
P
I/O
I/O
I/O
I/O
O
I
I/O
I/O
I
Ipu/O
Ipd/O
Ipd/O
Ipu/O
P
Ipd/O
O
Type
(1)
Pin Function
Ground
1.8V analog V
3.3V analog V
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode is selected.
Crystal / Oscillator / External Clock Input
MII Mode:
RMII Mode:
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041NL reference schematics.
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MII Mode:
Config Mode:
MII Mode:
Config Mode:
MII Mode:
RMII Mode:
Config Mode:
MII Mode:
RMII Mode:
Config Mode:
3.3V digital V
MII Mode:
RMII Mode:
Config Mode:
MII Mode:
DD
DD
DD
25MHz +/-50ppm (crystal, oscillator, or external clock)
50MHz +/-50ppm (oscillator, or external clock only)
Receive Data Output[3]
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[2]
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[1]
Receive Data Output[1]
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[0]
Receive Data Output[0]
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
Receive Data Valid Output /
Carrier Sense/Receive Data Valid Output /
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
Receive Clock Output
9
(2)
(2)
(2)
(3)
(2)
(3)
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M9999-071808-1.2
KSZ8041NL