KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 124

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Timing Specifications
Asynchronous Timing without using Address Strobe (ADSN = 0)
Micrel, Inc.
October 2007
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Note 1: When CPU finished current Read or Write operation, it can do next Read or Write operation even
Note 2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only
Addr, AEN, BExN
the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the
RDN/WRN low until the ARDY returns to high.
supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
(Read Cycle)
( Write Cycle)
RDN, WRN
Write Data
Read Data
Parameter
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
A1-A15, AEN, BExN[3:0] hold after RDN inactive
(assume ADSN tied Low)
A1-A15, AEN, BExN[3:0] hold after WRN inactive
(assume ADSN tied Low)
Read data valid to ARDY rising
Read data to hold RDN inactive
Write data setup to WRN inactive
Write data hold after WRN inactive
Read active to ARDY Low
Write inactive to ARDY Low
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
ADSN
ARDY
ARDY
Table 24. Asynchronous Cycle (ADSN = 0) Timing Parameters
Figure 17. Asynchronous Cycle – ADSN = 0
t1
124
t7
t9
valid
t3
t5
valid
Min
0
0
1
4
4
2
0
0
0
valid
KSZ8842-16/32 MQL/MVL/MVLI/MBL
t2
t6
Typ
t4
40
80
50
t8
t10
Max
0.8
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M9999-102207-1.9