KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 57

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Internal I/O Space Mapping (continued)
I/O Register Location
32-Bit
Micrel, Inc.
October 2007
0xC
0xB
0xF
0x0
0x3
0x4
0x7
0x8
To
To
To
To
16-Bit
- 0xD
- 0x1
- 0x3
- 0x5
- 0x7
- 0x9
- 0xB
- 0xF
0xA
0xC
0xE
0x0
0x2
0x4
0x6
0x8
8-Bit
0xC
0xD
0xA
0xB
0xE
0xF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
TOS Priority
Bank 40
Control 1
Control 1
Control 2
Control 2
Control 3
Control 3
Control 4
Control 4
Control 5
Control 5
Control 6
Control 6
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
TOS Priority
TOS Priority
TOS Priority
TOS Priority
Bank 41
Reserved
Reserved
Reserved
Reserved
Control 7
Control 7
Control 8
Control 8
[15:8]
[15:8]
[7:0]
[7:0]
Access Data 1
Access Data 1
Access Data 2
Access Data 2
Access Data 3
Access Data 3
Access Data 4
Access Data 4
Access Data 5
Access Data 5
Access Ctrl.
Access Ctrl.
Bank 42
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
Indirect
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
57
Bank 43
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bank Location
Bank Select [15:8]
Bank Select [7:0]
Reserved
Analog Test
Analog Test
Analog Test
Analog Test
Analog Test
Analog Test
Analog Test
Analog Test
Digital Test
Digital Test
Digital Test
Digital Test
Bank 44
Control 0
Control 0
Control 1
Control 1
Control 2
Control 2
Control
Control
Status
Status
Status
Status
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
KSZ8842-16/32 MQL/MVL/MVLI/MBL
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Basic Control
Basic Control
PHY1 PHYID
PHY1 PHYID
PHY1 PHYID
PHY1 PHYID
Basic Status
Basic Status
Link Partner
Link Partner
Ability [15:8]
Ability [7:0]
PHY1 A.N.
PHY1 A.N.
PHY1 A.N.
PHY1 A.N.
PHY1 MII-
PHY1 MII-
PHY1 MII-
PHY1 MII-
Bank 45
Register
Register
Register
Register
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
High
High
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Low
Low
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Basic Control
Basic Control
PHY2 PHYID
PHY2 PHYID
PHY2 PHYID
PHY2 PHYID
Basic Status
Basic Status
Ability [15:8]
Link Partner
Link Partner
PHY2 A.N.
PHY2 A.N.
PHY2 A.N.
Ability [7:0]
PHY2 A.N.
PHY2 MII-
PHY2 MII-
PHY2 MII-
PHY2 MII-
Bank 46
Register
Register
Register
Register
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
High
[7:0]
High
[7:0]
Low
Low
M9999-102207-1.9
PHY1 LinkMD
Control/Status
PHY1 LinkMD
Control/Status
Control/Status
Control/Status
PHY2 LinkMD
Control/Status
PHY2 LinkMD
Control/Status
Control/Status
Control/Status
PHY1 Special
PHY1 Special
PHY2 Special
PHY2 Special
Bank 47
Reserved
Reserved
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]