AT43USB320A_04 ATMEL [ATMEL Corporation], AT43USB320A_04 Datasheet - Page 32
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AT43USB320A_04
Manufacturer Part Number
AT43USB320A_04
Description
Full-speed USB Microcontroller with an Embedded Hub
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT43USB320A_04.pdf
(115 pages)
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USB Endpoint
Interrupt Sources
32
AT43USB320A
An assertion or activation of one or more bits in the endpoint's Control and Status Register
triggers the endpoint interrupts. These triggers are different for control and non-control end-
points as described in the table below. Please refer to the Control and Status Register for
more information.
Table 11. USB Endpoint Interrupt Sources
USB Interrupt Status Register – UISR
• Bit 7 – SOF INT: Start of Frame Interrupt
This bit is asserted after the USB hardware receives a valid SOF packet.
• Bit 6 – EOF2 INT: EOF2 Interrupt
This bit is asserted 10 clocks before the expected start of a frame.
• Bit 5, 4 – Res: Reserved Bits
These bits are reserved and always read as zero.
• Bit 3 – HEP0 INT: Hub Endpoint 0 Interrupt
• Bit 2 – FEP2 INT: Function Endpoint 2 Interrupt
• Bit 1 – FEP1 INT: Function Endpoint 1 Interrupt
• Bit 0 – FEP0 INT: Function Endpoint 0 Interrupt
The hub and function interrupt bits will be set by the hardware whenever the following bits in
the corresponding endpoint's Control and Status Register are modified by the USB hardware:
1. RX OUT Packet is set (control and OUT endpoints)
2. TX Packet Ready is cleared AND TX Complete is set (control and IN endpoints)
3. RX SETUP is set (control endpoints only)
4. TX Complete is set
Bit
RX_OUT_PACKET
TX_COMPLETE
STALL_SENT
RX_SETUP
Read/Write
Initial Value
$1FF7
Bit
SOF INT
R
7
0
EOF2 INT
6
R
0
R
5
–
0
R
4
–
0
HEP0 INT
R
3
0
Endpoint type
CONTROL, OUT
CONTROL, IN
CONTROL, IN
CONTROL
FE2 INT
R
2
0
FE1 INT
R
1
0
FE0 INT
1443E–USB–4/04
R
0
0
UISR
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