AT43USB320A_04 ATMEL [ATMEL Corporation], AT43USB320A_04 Datasheet - Page 59

• Manufacturer Part Number: AT43USB320A_04
• Description: Full-speed USB Microcontroller with an Embedded Hub
• Manufacturer: ATMEL [ATMEL Corporation]

Data Reception
1443E–USB–4/04
Figure 19. UART Transmitter
Figure 20 shows a block diagram of the UART Receiver.
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the
baud rate. While the line is idle, one single sample of logical "0" will be interpreted as the fall-
ing edge of a start bit and the start bit detection sequence is initiated. Let sample 1 denote the
first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at samples
8, 9 and 10. If two or more of these three samples are found to be logical "1"s, the start bit is
rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is per-
formed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at
least two of the three samples is taken as the bit value. All bits are shifted into the Transmitter
Shift register as they are sampled. Sampling of an incoming character is shown in Figure 19.
When the stop bit enters the receiver, the majority of the three samples must be "1" to accept
the stop bit. If two or more samples are logical "0's, the Framing Error (FE) flag in the UART
Status Register (USR) is set. Before reading the UDR register, the user should always check
the FE bit to detect framing errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is
transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate reg-
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