STPCI0180BTC3 STMICROELECTRONICS [STMicroelectronics], STPCI0180BTC3 Datasheet - Page 26

• Manufacturer Part Number: STPCI0180BTC3
• Description: PC Compatible Embedded Microprocessor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PIN DESCRIPTION
3.2.10 PCMCIA INTERFACE
RESET Card Reset. This output forces a hard
reset to a PC Card.
A[25:0] Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0] I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
CA[25-0] Card Address . Used with the lower 11
bits of the ISA Address Bus to generate the Card
Address.
IORD# I/O Read. This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR# I/O Write . This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP Write Protect. This input indicates the status
of the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2 Battery Voltage Detect. These in-
puts will be generated by memory PC Cards that
include batteries and are an indication of the con-
dition of the batteries. BVD1 and BVD2 are kept
asserted high when the battery is in good condi-
tion.
READY#/BUSY#/IREQ# Ready/busy/Interupt re-
quest. This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
WAIT# Bus Cycle Wait. This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE# Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
26/55
(Combined with PCI / Cardbus)
Issue 1.1
WE#/PRGM# Write Enable. This output is used by
the host for gating Memory Write data. WE# is
also used for memory PC Cards that have pro-
grammable memory.
REG# Attribute Memory Select. This output is in-
active (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only re-
spond to IORD# or IOWR# when REG# is active
(low). Also see Section 3.2.6
CD1#, CD2# Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2# Card Enable . These are active low
output signals provided from the PCIC. CE#1 ena-
bles even Bytes, CE#2 odd Bytes.
ENABLE# Enable. This output is used to activate/
select a PC Card socket. ENABLE# controls the
external address buffer logic.C card has been de-
tected (CD#1 and CD#2 = ’0’).
ENIF# ENIF . This output is used to activate/select
a PC Card socket.
EXT_DIR EXternal Transreceiver Direction Con-
trol. This output is high during a read and low dur-
ing a write. The default power up condition is write
(low). Used for both Low and High Bytes of the
Data Bus.
VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0,
VPP2_EN1 Power Control. Five output signals
used to control voltages (VPP1, VPP2 and VCC)
to a PC Card socket. Also see Section 16.7.5
GPI# General Purpose Input. This signal is hard-
wired to 1.