STPCI0180BTC3 STMICROELECTRONICS [STMicroelectronics], STPCI0180BTC3 Datasheet - Page 27

• Manufacturer Part Number: STPCI0180BTC3
• Description: PC Compatible Embedded Microprocessor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

3.2.11 CARDBUS INTERFACE
For card bus pinouts, refer to the PCI pinout.
3.2.12 PCI INTERFACE
AD[31:0] PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
BE[3:0]# Bus Commands/Byte Enables. These
are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Industrial owns the bus and out-
puts when the STPC Industrial owns the bus.
FRAME# Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Industrial
owns the PCI bus.
TRDY# Target Ready. This is the target ready sig-
nal of the PCI bus. It is driven as an output when
the STPC Industrial is the target of the current bus
transaction. It is used as an input when STPC In-
dustrial initiates a cycle on the PCI bus.
IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Industrial initiates a bus cycle on the
PCI bus. It is used as an input during the PCI cy-
cles targeted to the STPC Industrial to determine
when the current PCI master is ready to complete
the current transaction.
STOP# Stop Transaction. STOP# is used to im-
plement the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Industrial and is used
as an output when a PCI master cycle is targeted
to the STPC Industrial.
(Combined with PCI / PCMCIA)
Issue 1.1
DEVSEL# I/O Device Select. This signal is used
as an input when the STPC Industrial initiates a
bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output
either when the STPC Industrial is the target of the
current PCI transaction or when no other device
asserts DEVSEL# prior to the subtractive decode
phase of the current PCI transaction.
PAR Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE[3:0]#,
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of the AD bus delayed by one PCI clock
cycle)
SERR# System Error. This is the system error sig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC In-
dustrial initiated PCI transaction. Its assertion by
either the STPC Industrial or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.
LOCK# PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
PCI_REQ#[2:0] PCI Request. These pins are the
three external PCI master request pins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
PCI_GNT#[2:0] PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCI_REQ#.
PCI_INT[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals. They are to be en-
coded before connection to the STPC Industrial
using ISACLK and ISACLKX2 as the input selec-
tion strobes.
3.2.13 MONITOR INTERFACE
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog color outputs from the RAMDACs
VSYNC Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
PIN DESCRIPTION
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