PIC10F220EOT MICROCHIP [Microchip Technology], PIC10F220EOT Datasheet - Page 12

• Manufacturer Part Number: PIC10F220EOT
• Description: 6-Pin, 8-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC10F220/222
FIGURE 3-1:
TABLE 3-1:
DS41270B-page 10
GP0/AN0/ICSPDAT
GP1/AN1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/V
V
V
Legend:
DD
SS
Program
Name
Bus
I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Input
PP
Instruction Reg
512 x 12 or
Generation
Instruction
256 x 12
Decode &
Program
Memory
12
Control
PINOUT DESCRIPTION
Timing
Flash
BLOCK DIAGRAM
Function
ICSPDAT
ICSPCLK
F
T0CKI
MCLR
GP0
GP1
GP2
GP3
AN0
AN1
V
OSC
V
V
8
DD
9-10
PP
SS
4
MCLR
Direct Addr
Device Reset
Program Counter
Internal RC
Watchdog
Power-on
Clock
Timer
Reset
Timer
STACK1
STACK2
Input
Type
TTL
TTL
TTL
TTL
AN
ST
AN
ST
ST
ST
HV
V
—
P
P
DD
, V
SS
5
Output
CMOS
CMOS
CMOS
CMOS
CMOS
Type
RAM Addr
—
—
—
—
—
—
—
—
—
Preliminary
8
3
Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
Analog Input
In-Circuit programming data
Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
Analog Input
In-Circuit programming clock
Bidirectional I/O pin
Clock input to TMR0
Oscillator/4 output
Input pin. Can be software programmed for internal weak pull-up and
wake-up from Sleep on pin change.
Master Clear (Reset). When configured as MCLR, this pin is an
active-low Reset to the device. Voltage on MCLR/V
exceed V
Programming mode. Weak pull-up always on if configured as MCLR.
Programming voltage input
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
Data Bus
Registers
23 or 16
Addr MUX
W Reg
ALU
bytes
RAM
File
STATUS Reg
FSR Reg
Timer0
5-7
9
MUX
DD
Indirect
Addr
during normal device operation or the device will enter
8
Absolute
Voltage
Reference
Description
GPIO
ADC
© 2006 Microchip Technology Inc.
GP0/AN0/ICSPDAT
GP1/AN1/ICSPCLK
GP2/T0CKI/F
GP3/MCLR/V
AN0
AN1
PP
must not
OSC
PP
4