PIC10F220EOT MICROCHIP [Microchip Technology], PIC10F220EOT Datasheet - Page 37

• Manufacturer Part Number: PIC10F220EOT
• Description: 6-Pin, 8-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 8-2:
8.3.1
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
FIGURE 8-1:
8.4
The PIC10F220/222 devices incorporate an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
V
ation. To take advantage of the internal POR, program
the GP3/MCLR/V
resistor to V
weak pull-up resistor is implemented using a transistor
(refer to Table 10-2 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V
acteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
© 2006 Microchip Technology Inc.
MCLRE
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset during Sleep
WDT Reset normal operation
Wake-up from Sleep on pin change
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.
DD
DD
DD
GPWU
and the pin is assigned to be a I/O. See Figure 8-1.
has reached a high enough level for proper oper-
is specified. See Section 10.0 “Electrical Char-
Power-on Reset (POR)
MCLR ENABLE
DD
, or program the pin as GP3. An internal
PP
RESET CONDITION FOR SPECIAL REGISTERS
pin as MCLR and tie through a
MCLR SELECT
GP3/MCLR/V
Weak Pull-up
Internal MCLR
PP
Preliminary
STATUS Addr: 03h
0--1 1xxx
0--u uuuu
0--1 0uuu
0--0 0uuu
0--0 uuuu
1--1 0uuu
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-2.
The Power-on Reset circuit and the Device Reset
Timer (see Section 8.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 1.125 ms, it will reset
the Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 8-3. V
bringing MCLR high. The chip will actually come out of
Reset T
In Figure 8-4, the on-chip Power-on Reset feature is
being used (MCLR and V
is programmed to be GP3). The V
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-5 depicts a
problem situation where V
between when the DRT senses that MCLR is high and
when MCLR and V
too long. In this situation, when the start-up timer times
out, V
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-4).
For additional information, refer to Application Notes
AN522, “Power-Up Considerations” (DS00522) and
AN607, “Power-up Trouble Shooting” (DS00607).
Note:
DD
DRT
has not reached the V
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
msec after MCLR goes high.
DD
PIC10F220/222
is allowed to rise and stabilize before
DD
actually reach their full value, is
DD
DD
are tied together or the pin
PCL Addr: 02h
rises too slowly. The time
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
DD
(min) value and the
DD
DS41270B-page 35
is stable before