CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 23

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Programming Specifications
Document Number: 001-69257 Rev. *F
t
t
t
t
F
t
t
t
t
t
t
t
t
t
t
t
t
Note
RSCLK
FSCLK
SSCLK
HSCLK
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
XRST3
XRES
VDDWAIT
VDDXRES
POLL
ACQ
XRESINI
30. Valid from 5 to 50 °C. See the spec,
SCLK
Symbol
CY8C20X47, CY8C20X37, Programming Spec
[30]
[30]
[30]
[30]
SCLK (P1[1])
SDATA (P1[0])
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK –
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK 3.6  V
Data out delay from falling edge of SCLK 3.0  V
Data out delay from falling edge of SCLK 1.71  V
External reset pulse width after power-up Required to enter programming
XRES pulse length
V
V
SDAT high pulse time
“Key window” time after a V
acquire event, based on 256 ILO clocks.
“Key window” time after an XRES event,
based on 8 ILO clocks
DD
DD
stable to wait-and-poll hold off
stable to XRES assertion delay
T
RSCLK
Description
CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67,
T
SSCLK
for more details.
DD
T
ramp
FSCLK
Figure 10. AC Waveform
T
HSCLK
–
–
–
–
–
mode when coming out of sleep
–
–
–
–
–
–
–
DD
DD
DD
 3.6
Conditions
 3.0
CY8C20x37/37S/47/47S/67/67S
T
14.27
DSCLK
0.01
3.20
Min
300
300
0.1
40
40
98
1
1
0
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
19.60
Max
130
200
615
20
20
18
25
60
85
–
–
8
–
–
1
–
Page 23 of 39
Units
MHz
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
s
s
s